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Method and Circuits for Optimizing Response Time in Hardware Implementation of Neural Network Algorithms

IP.com Disclosure Number: IPCOM000014472D
Original Publication Date: 2000-Feb-01
Included in the Prior Art Database: 2003-Jun-19
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Abstract

Method and Circuits for Optimizing Response Time in Hardware Implementation of Neural Network Algorithms

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Method and Circuits for Optimizing Response Time in Hardware

Implementation of Neural Network Algorithms

 Prototype component 1

 Prototype component 2

 Prototype component n

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Host

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on nneurneuron 2neuron 1memory

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distance 1

FIG. 1a

Disclosed is a pipe-line method and circuits associated thereto to reduce the response time of input space mapping based neural network processing. While the input vector components are fed into the system and the distances are calculated, the system sorts the previous computed distances. When all the components have been fed into the system, the distances have been calculated and the previous computed distances have been sorted, the microprocessor interface is used to send the results to the host. An improvement of this method consists in feeding the components more than once at a time. The components are fed into the system and stored in a global memory to be processed one at a time. This second embodiment allows to release the microprocessor interface sooner thus increasing the time assigned to transfer the results to the host.

   Fig. 1a and 1b illustrate an example of a circuit that can be used to implement this method. Fig. 1a is the scheme of the full system, containing the memory used to store the components and the neurons that are used to memorize the prototypes, compute the distances between these prototypes and the input vector and to sort the resulting distances. A selector is used to set the microprocessor inte...