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Browse Prior Art Database

Dynamic Memory Allocation Based on a Stride-Based Addressing Scheme for Accessing Buffers

IP.com Disclosure Number: IPCOM000014515D
Original Publication Date: 2001-Apr-15
Included in the Prior Art Database: 2003-Jun-19
Document File: 3 page(s) / 66K

Publishing Venue

IBM

Abstract

Objective Conventional memory management schemes allocate memory as blocks of contiguous addresses which can be chained together by storing pointers in these buffers or in control blocks associated with these buffers, in order to form larger blocks of storage. The pointers that are used for chaining can be a significant overhead for applications that only use small buffers (e.g., buffers of only a few bytes), because the storage required by these pointers cannot be neglected against the buffer size. The disclosed idea has the objective to reduce this overhead. The idea involves a memory management scheme that uses a mapping function to chain buffers instead of chaining buffers together using pointers.

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  Dynamic Memory Allocation Based on a Stride-Based Addressing Scheme for Accessing Buffers

Objective

Conventional memory management schemes allocate memory as blocks of contiguous addresses which can be chained together by storing pointers in these buffers or in control blocks associated with these buffers, in order to form larger blocks of storage.

The pointers that are used for chaining can be a significant overhead for applications that only use small buffers (e.g., buffers of only a few bytes), because the storage required by these pointers cannot be neglected against the buffer size.

The disclosed idea has the objective to reduce this overhead. The idea involves a memory management scheme that uses a mapping function to chain buffers instead of chaining buffers together using pointers.

Description

Figure 1 shows two examples to illustrate the concept of the disclosed idea.

Figure 1 (a) shows a memory in which the four marked memory locations form one buffer. The four successive memory locations are located at addresses ' 1000h' (hexadecimal), '1008h', '1010h', and ' 1018h' which involve a fixed incremental step
(i.e., stride) equal to 8. These four memory locations can be chained into one buffer by specifying the stride together with the pointer to the first of these locations (assuming that the buffer size of 4 locations is known to the application). The address of the

k

th

memory location within the buffer (where k equals 1,2,3, or 4) is given by:

address = (k-1) x stride + pointer = (k-1) x 8 + 1000h

...