Browse Prior Art Database

Digital link eye analysis using phase rotator means

IP.com Disclosure Number: IPCOM000014574D
Original Publication Date: 2001-Apr-01
Included in the Prior Art Database: 2003-Jun-19
Document File: 2 page(s) / 60K

Publishing Venue

IBM

Abstract

The novel contribution provided by this concept is a method of analyzing high speed links in the application environment without expensive test equipment and without special card considerations by using a phase rotator to allow the sample window to be moved in small steps across the receive "eye". Manual controls for the phase rotator are provided by the core as well as a sample data access interface. See the attached figure for the flow of the invention. This invention uses circuit elements already in place to step through a number of settings related to the position of sampling clock phases. These phases are normally used to detect bit edge information and position a sampling pulse at the appropriate time for getting correct data. The invention uses a device called a phase rotator (subject of previous invention disclosure) to step phases through a predetermined sequence of arbitrarily small steps. This phase rotator is an analog circuit element which consists of an finite impulse response filter (FIR) having as input a number of phases and as output a shifted (same) number of phases. As one changes weighting in this FIR the output phase is shifted. This property is used in this invention to discern a sampling "eye" width by first initializing the rotator to a known position, then capturing the sample data, then storing the sample data, then stepping the phase by the appropriate amount as per the architecture. After stepping through all phase steps and storing the data, the data value versus phase step position is computed via post processing of the data to obtain the "eye" opening versus time as indicated by the data value for each time step. This data “eye” information may be used instantaneously to determine the instantaneous "eye" shape or it may be stored and averaged by an algorithm to study data "eye" width versus time. This can be a valuable indicator of ongoing, average link performance and may be used to head off problems in a preemptive fashion by examining the “eye” statistics over time. The flow chart in the attached figure depicts this process pictorially. 1 I n it ia liz e positions of the p h a s e r o ta to r Translate n-m bit R A in d e x to n -b it default index

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 59% of the total text.

Page 1 of 2

Digital link eye analysis using phase rotator means

  The novel contribution provided by this concept is a method of analyzing high speed links in the application environment without expensive test equipment and without special card considerations by using a phase rotator to allow the sample window to be moved in small steps across the receive "eye". Manual controls for the phase rotator are provided by the core as well as a sample data access interface. See the attached figure for the flow of the invention. This invention uses circuit elements already in place to step through a number of settings related to the position of sampling clock phases. These phases are normally used to detect bit edge information and position a sampling pulse at the appropriate time for getting correct data. The invention uses a device called a phase rotator (subject of previous invention disclosure) to step phases through a predetermined sequence of arbitrarily small steps. This phase rotator is an analog circuit element which consists of an finite impulse response filter (FIR) having as input a number of phases and as output a shifted (same) number of phases. As one changes weighting in this FIR the output phase is shifted. This property is used in this invention to discern a sampling "eye" width by first initializing the rotator to a known position, then capturing the sample data, then storing the sample data, then stepping the phase by the appropriate amount as per the architecture....