Browse Prior Art Database

Method for controlling PLL through JTAG interface

IP.com Disclosure Number: IPCOM000014616D
Original Publication Date: 2001-Apr-22
Included in the Prior Art Database: 2003-Jun-20
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Abstract

In the original and follow-on releases of the JTAG control macro, many of the custom VLSI chips used in AS/400* systems, the control macro referred to as the "ACCESS" macro, the on-chip Phase Lock Loop (PLL) clock generator control were from chip primary input, or directly with latches which were themselves clocked by the clock output of the PLL. The programmable control to the PLL includes, the multiplier, the range, and the tune which are used in combination to provide a wide range of output clock frequencies while accepting a wide range of reference clock frequencies. The significant number PLL controls using Primary Input to the chip is not always desirable; in cases where the pins would otherwise be utilized by the chip's marketable function demanded by the paying customer; and in programmable or fusible latches internal to the chip must set. However, there is a potential problem with using latches clocked by the PLL to control the PLL. Changing the input to the PLL could create a change in the clock which may lead to an alterating of the values in the latches providing the PLL controls. It is valid to assume that the PLL would always be generating some clock output, whether in the "BYPASS" mode or not. In the "BYPASS" mode, the slower speed reference clock into the chip gets muxed to the clock output, bypassing the PLL function. When not in the "BYPASS" mode, the PLL will generate an output clock which is at a multiple of the reference clock. During Power-On, the PLL is forced into "BYPASS" mode to ensure a steady clock to reset the latches controlling the PLL. To ensure that the controls for the PLL do not change as the PLL output clock frequency is changed, the controls are moved to "Option Registers" in the ACCESS macro itself. The key benefit for using the Option Registers is that the Option Registers are clocked with the slow JTAG "TCK" clock. The operation of the TCK clock and the writing of the Option Register are defined in the 1149.1 IEEE JTAG specification... The PLL control bits are assigned to be bits of the Option Registers. These bits of the Option Registers controlling the PLL are made to also be "FIXED-VALUE" during LSSD Test Mode. Note that is important not to observe the "FIXED-VALUE" latches during the LSSD test mode to ensure that the same test patterns may be used over a wide range of PLL control settings. Additionally, SET/RESET latch commands were added to the ACCESS macro. The ACCESS macro uses the TCK clock as its only clock. One of these SET/RESET latch commands was designated to issue a "RESET" to the clocking control logic receiving the PLL clock output. This enables resetting the clocking control logic after the PLL multiplier, range, and tune settings have been initialized.

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Method for controlling PLL through JTAG interface

In the original and follow-on releases of the JTAG control macro, many of the custom VLSI chips used in AS/400* systems, the control macro referred to as the "ACCESS" macro, the on-chip Phase Lock Loop (PLL) clock generator control were from chip primary input, or directly with latches which were themselves clocked by the clock output of the PLL. The programmable control to the PLL includes, the multiplier, the range, and the tune which are used in combination to provide a wide range of output clock frequencies while accepting a wide range of reference clock frequencies. The significant number PLL controls using Primary Input to the chip is not always desirable; in cases where the pins would otherwise be utilized by the chip's marketable function demanded by the paying customer; and in programmable or fusible latches internal to the chip must set. However, there is a potential problem with using latches clocked by the PLL to control the PLL. Changing the input to the PLL could create a change in the clock which may lead to an alterating of the values in the latches providing the PLL controls. It is valid to assume that the PLL would always be generating some clock output, whether in the "BYPASS" mode or not. In the "BYPASS" mode, the slower speed reference clock into the chip gets muxed to the clock output, bypassing the PLL function. When not in the "BYPASS" mode, the PLL will generate an output clock which is at a multiple of the reference clock. During Power-On, the PLL is forced into "BYPASS" mode to ensure a steady clock to reset the latches controlling the PLL. To ensure that the controls for the PLL do not change as the PLL output clock frequency is changed, the controls are moved to "Option Registers" in the ACCESS macro itself. The key benefit for using the Option Registers is that the Option Registers are clocked with the slow JTAG "TCK" clock. The opera...