Browse Prior Art Database

Method and Apparatus for the Placement of Signals Onto Lanes of a Byte Lane Selectable Bus to Provide Maximum Flexibility in Selecting Signal Groups

IP.com Disclosure Number: IPCOM000014687D
Original Publication Date: 2001-Jun-10
Included in the Prior Art Database: 2003-Jun-20
Document File: 7 page(s) / 117K

Publishing Venue

IBM

Abstract

Method and Apparatus for the Placement of Signals Onto Lanes of a Byte Lane Selectable Bus to Provide Maximum Flexibility in Selecting Signal Groups

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 38% of the total text.

Page 1 of 7

Method and Apparatus for the Placement of Signals Onto Lanes of a Byte Lane

Selectable Bus to Provide Maximum Flexibility in Selecting Signal Groups

   The use of a programmable, byte lane selectable bus requires that the placement of the various processor units/signals be assigned to byte lanes/bit positions of the bus so that required signal groups can be observed concurrently. The method of this disclosure is an interative process which produces a solution accommodating the maximum number of required groups within the constraints of the byte lane selectable bus design.

   The method for optimizing signal placement on the bus considers the constraints of the byte lane selectable bus, the signal groups required for analysis, and the signal placement necessary to support that analysis. The method involves several steps which generally are described as chosing activities to be anaylzed, identifying the signals needed for the analysis, forming groups of signals for the analysis areas, arranging units across the bus input muxes to support the groups, placing groups of signals onto the mux byte lanes for each unit, and assigning each signal in a byte lane to a specific bit position. The details of these steps are now presented together with the tools and techniques developed for the method of this disclosure.

1. Choose the activities that are to be analyzed.

An example of activities might include:

overall processor performance

instruction flow in the processor

data flow in the processor

memory nest untilzation

load/store queue occupancy

prefetch mechanism activity

floating point efficiency

fixed point busy/idle ratios

2. Identify the signals needed to support each analysis area; these signals may come from several different sourcing units. An example of signals needed to study floating point activity might include: signal for when a floating point arithmetic operation is performed

signal for when a floating point microcoded instruction executes

signal for when a floating point stall occurs

signal for when the floating point issue queue is full

signal for when a floating point load operation executes

signal for when a floating point store operation executes

3. Make general groups of signals for each area of the analysis.

An example of signals that could be considered together to analyze poor performance might include:

tablewalk duration

resource 'fullness'

1

Page 2 of 7

l1 reload data source

l1 icache data source

l1 dcache store miss

erat misses

flushes due to unaligned loads/stores

tlb misses

slb misses

4. Based on the signal groups chosen in 3. use the TTM worksheet developed by the method to decide which units have to be accessed together. An example of unit constraint analysis using the TTM worksheet where the bus muxes/lanes are assigned to example units (referred to as isuxx, fpuxx, ifuxx, lsuxx, iduxx for the purposes of the example) so that units that must be viewed together do not collide (ex. isuxx 'fullness' signals in TTM0, iduxx...