Browse Prior Art Database

Method for System On Chip timing analysis

IP.com Disclosure Number: IPCOM000014748D
Original Publication Date: 2001-Apr-22
Included in the Prior Art Database: 2003-Jun-20
Document File: 3 page(s) / 44K

Publishing Venue

IBM

Abstract

System On Chip (SOC) refers to large chips which include several functional units such as a processor core and memory subsystem which in the past would have resided in separate chips.

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Method for System On Chip timing analysis

System On Chip (SOC) refers to large chips which include several functional units such as a processor core and memory subsystem which in the past would have resided in separate chips.

One consequence of these large chips is that they have a lot of timing paths. Timing paths are measurements of how long it takes an electrical signal to travel from the start of an electronic circuit, until it reaches the end of the circuit. The start of a timing path can be a storage element such as a latch. The data output of this latch usually connected to a series of electronic circuits and the result of this circuit is usually captured by another storage element such as a latch. This is where the timing path usually ends.

It is important that these timing paths arrive at a certain time so that the capture latch can sample the result of the circuit. This is the main reason that a chip can run at certain clock frequency.

During chip development, every possible timing path is measured and reported using a "Static Timing" tool such as Einstimer or Pathmill. These tools will print a report, which by nature of SOC, is very large. The job of the design engineer is to look through the report and fix timing paths by changing the circuit that does not meet clock frequency.

The job of an engineer is harder when buses are present in the design. Buses are a collection of signals that represent a unit of data. Circuitry on one of the bus signals is usually the same for all other signals. The bus designs are done by using common blocks which have the same circuitry and is replicated for each signal.

Static timing reports which contains buses are very large, because each signal of the bus is considered a timing path and reported separately. Having the engineer work through all paths, is an enormous task. However, in the course of the design cycle, reports are generated to test each new circuit change for a new timing solution. This could be as frequent as once a day and would add up to hundreds or even more total reports during the entire project. Moreover, an engineer has to analyze all this data, and cannot look through all the reports in a fast and efficient manner.

This invention is a methodology with an algorithm for a tool that will help the engineer process and analyze the large Static timing report. The methodology is a new way of reducing the number of paths that engineers need to analyze using a new tool. This tool works by identifying buses as unique paths using the algorithm of this invention.

The result of this tool is a simplified summary report of all "unique" timing paths. This summary report will have references to the large Static timing report, how much time is the path missing, description of the path. Buses will be counted as one unique path. Example of report:

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