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DRAM Refresh Rate Control Using Battery Voltage

IP.com Disclosure Number: IPCOM000014757D
Original Publication Date: 2000-May-01
Included in the Prior Art Database: 2003-Jun-20
Document File: 1 page(s) / 28K

Publishing Venue

IBM

Abstract

Disclosed is a system capable of controlling the data retention power of Dynamic Random Access Memory (DRAM) by changing its refresh rate as a function of battery voltage in a more intelligent and adaptive manner.

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DRAM Refresh Rate Control Using Battery Voltage

Disclosed is a system capable of controlling the data retention power of
Dynamic Random Access Memory (DRAM) by changing its refresh rate as a function
of battery voltage in a more intelligent and adaptive manner.

Many battery-operated computer devices, such as Personal Digital Assistance
(PDA) devices, recently use DRAM as their persistent storage. Because DRAM
needs to be periodically refreshed to retain its contents, users have an
"empty-battery" risk, that is the risk of losing the entire contents in the
persistent storage when battery becomes empty. On the other hand, since the
refresh operation drains some current, the battery power consumption is
reduced by reducing the DRAM refresh rate at "potential retention failure"
risk, the risk of losing a very small part of the contents. Our idea proposes
to balance and optimize these two inherent risks in the DRAM-based persistent
storage.

This invention provides a system that controls DRAM refresh rate, in a
risk-optimized manner, as a function of the battery voltage. A typical
implementation of the proposed system consists of DRAM, a DRAM control circuit
(responsible for the refresh operation), and a battery, and a battery voltage
measurement unit. The DRAM control circuit periodically asks to measure the
battery voltage, and chooses an optimal value of the DRAM refresh rate. When
the battery voltage becomes lower than a specified value, indicating that
"empty-battery" risk becomes...