Browse Prior Art Database

AC SCAN DIAGNOSTIC METHOD Disclosure Number: IPCOM000014782D
Original Publication Date: 2000-Oct-18
Included in the Prior Art Database: 2003-Jun-20
Document File: 6 page(s) / 84K

Publishing Venue




This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 18% of the total text.

Page 1 of 6



This invention disclosure proposes a solution to the problem of testing and rapidly diagnosing AC scan chain defects and localizing these defects to a failing Shift Register Latch (SRL) or associated scan clock tree. This on-the-fly quick and accurate pinpointing of systematic and random circuit faults can be performed during the test process of most scan based designs. The concept can be further enhanced and extended to diagnose similar AC defects encountered in BIST structures incorporating On-Product Clock Generation (OPCG) support.

These type of problems are usually encountered early in the technology's life cycle and their diagnosability is critical in improving the process so it quickly achieves manufacturing yield levels. An inability to improve the technology and yield of the device can greatly impact a program or at least severely minimize the revenue that could be realized. Rapid diagnosis to a location for Physical Failure Analysis (PFA) is needed to understand and correct the process anomalies.

Figures and Drawings

Double click on the following icon and select launch to display all figures referred to in this disclosure. You can then switch back and forth between the disclosure text and the corresponding figures.

AC_Diagnostic_Method.p Background Information

Before describing the solution to the problem referenced above we shall give a short overview of the scan based design and test methodology. Specifically, we shall discuss the LSSD [Ref. 1-3] as practiced in most IBM chip and system designs, although many of the basic concepts apply to other variations of scan designs.

The LSSD methodology is a system design and a Design-for-Test (DFT) approach that incorporates several basic test concepts, i.e. scan design. In such a design most of the device's storage elements, such as latches or registers are concatenated in one or more scan chains and can be externally accessible via one or more serial inputs and outputs. Storage elements that are not in this category are usually memory or other special macros that are isolated and tested independently. Furthermore, this design methodology ensures that all logic feedback paths are gated by one or more of these storage elements, thereby simplifying a sequential design into subsets of combinational logic sections as shown in Fig. 1and Fig. 2.

These basic design concepts in conjunction with the associated system and scan clocking sequences greatly simply the test generation, testing, and diagnosability of very complex logic structures. Every latch can be used as a pseudo Primary Input (PI) and as a pseudo Primary Output (PO) in addition to the standard PIs and POs to enhance the stimulation and observability of the device being tested or diagnosed. LSSD latches are typically implemented in a L1/L2 configuration where the L1 or master latch has two data ports and may be updated be either a scan clock or a functional clock. The L2 or slave latch has...