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Representation of on-chip noise sources by simple equivalent circuits

IP.com Disclosure Number: IPCOM000014813D
Original Publication Date: 2001-Dec-01
Included in the Prior Art Database: 2003-Jun-20
Document File: 1 page(s) / 33K

Publishing Venue

IBM

Abstract

On-chip switching of circuits is the physical part of the execution of logic operation sequences. Power dissipation and electrical noise are by-products of the switching activity. Clock trees, clock splitters and front stages of latches run continuously, consuming power and creating switching noise. The switching noise may become superimposed on ground, power rail and signal levels, both on-chip and off-chip. For this reason it is necessary to simulate the noise, and if the results suggest, make design changes to reduce it. The simulation can also make an important contribution to chip power estimation. Using the actual circuits would result in a very large ASX or HSPICE deck that would require large memory and storage space and long running times. This invention shows how the same results may be obtained by a smaller, equivalent model. C locks are generally distributed over the entire chip, but not uniformly. Some areas on chip are more heavily populated than others, these are the areas to be modelled. The smallest repeatable subset of the chip image should be used for the model area. This allows some simplifying assumptions to be made and reduces the number of power distribution components that have to be included in the model. This is one step towards making the model small and the analysis quick. Representation of the switching components: The large number of noise generating components are represented by a few large inverters and appropriately assigned load capacitances. The total w/l of the replacement inverter FETs is made equal to the total w/l of the FETs found in the complex clock network. In a particular implementation 20 large inverters are used to create the noise that would be generated by the clock and latch components representing a typical placement density on 1.2 sq.mm of the chip. The 20 inverters are arranged in five stages that mimic the timing distribution of the switching activity. Load capacitances can be based on historical or extracted data. Representation of the non-switching components: The non-switching circuits form decoupling capacitances which are included in the model. Their value is calculated from the total junction and gate capacitances of the non-switching circuits, based on the model area.

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Representation of on-chip noise sources by simple equivalent circuits

On-chip switching of circuits is the physical part of the execution of logic operation sequences. Power dissipation and electrical noise are by-products of the switching activity. Clock trees, clock splitters and front stages of latches run continuously, consuming power and creating switching noise. The switching noise may become superimposed on ground, power rail and signal levels, both on-chip and off-chip. For this reason it is necessary to simulate the noise, and if the results suggest, make design changes to reduce it. The simulation can also make an important contribution to chip power estimation. Using the actual circuits would result in a very large ASX or HSPICE deck that would require large memory and storage space and long running times. This invention shows how the same results may be obtained by a smaller, equivalent model.

Clocks are generally distributed over the entire chip, but not uniformly. Some areas on chip are more heavily populated than others, these are the areas to be modelled. The smallest repeatable subset of the chip image should be used for the model area. This allows some simplifying assumptions to be made and reduces the number of power distribution components that have to be included in the model. This is one step towards making the model small and the analysis quick.

Representation of the switching components: The large number of noise generating components are...