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Methodology for Detecting Un-programmed Programmable Logic Module

IP.com Disclosure Number: IPCOM000014822D
Original Publication Date: 2000-Jan-01
Included in the Prior Art Database: 2003-Jun-20
Document File: 2 page(s) / 54K

Publishing Venue

IBM

Abstract

During computer development, problems in a complex high density logic chip are often discovered late in the development cycle. Fixing the complex high density logic chip would take a long time, specially the turn around time of the wafer silicon; therefore, it would impact the project schedule. To maintain on schedule, a programmable logic array is used to provide a work around solution to the problems found in the complex logic chips. Logic errors in the complex logic chip fall into two broad categories: first, those that easily detected, e.g. system will not start; and second, those that cause subtle failures that may go undetected, e. g. a wrong cache line being returned causing a data error. This disclosure relates to the second type of logic error and how to make sure it is corrected. In the particular case, we have a logic error that causes a wrong cache line 32 byte quantity) to be accessed when an unique three-way address collision occurs. A programmable array logic (PAL) module is included to modify associated cycles on the appropriate bus to avoid the error occurring in the complex logic chip. During the manufacturing process, if the programming of the programmable array logic (PAL) module is skipped, for example the PAL is not programmed due to human error, the system will still perform adequately but will fail when the unique three-way address collision occurs. To test for the presence of correct code in the programmed programmable array logic (PAL) module, this disclosure uses the fact that when the PAL module is working, the system performance is degraded and this difference can be measured whenever the computer starts. If the PAL module is not programmed, there is no easy way to detect this apart from examining outputs for correct operation or by reading the programmable logic internal bit map for the correct data, or by replacing the component with a known programmed part. If a computer makes through the manufacturing process with a blank programmable part, the customer impact is large since the, machine must be opened and fixed by programming the logic or replacing it. This disclosure defined an emgineering software built-in test code to check that the PAL module is correctly functioning, hence programmed.

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Methodology for Detecting Un-programmed Programmable Logic Module

During computer development, problems in a complex high density logic chip are often discovered late in the development cycle. Fixing the complex high density logic chip would take a long time, specially the turn around time of the wafer silicon; therefore, it would impact the project schedule. To maintain on schedule, a programmable logic array is used to provide a work around solution to the problems found in the complex logic chips. Logic errors in the complex logic chip fall into two broad categories: first, those that easily detected, e.g. system will not start; and second, those that cause subtle failures that may go undetected, e. g. a wrong cache line being returned causing a data error.

This disclosure relates to the second type of logic error and how to make sure it is corrected. In the particular case, we have a logic error that causes a wrong cache line ( 32 byte quantity) to be accessed when an unique three-way address collision occurs. A programmable array logic (PAL) module is included to modify associated cycles on the appropriate bus to avoid the error occurring in the complex logic chip.

During the manufacturing process, if the programming of the programmable array logic (PAL) module is skipped, for example the PAL is not programmed due to human error, the system will still perform adequately but will fail when the unique three-way address collision occurs. To test for the presenc...