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Method for Pre-processing Netlist and Test Models which Synchronizes I/O for Proper Automatic Test Pattern Generation for Multi-Phase Circuits

IP.com Disclosure Number: IPCOM000014829D
Original Publication Date: 2001-Jul-01
Included in the Prior Art Database: 2003-Jun-20
Document File: 5 page(s) / 53K

Publishing Venue

IBM

Abstract

Method for Pre-processing Netlist and Test Models which Synchronizes I/O for Proper Automatic Test Pattern Generation for Multi-Phase Circuits

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Method for Pre-processing Netlist and Test Models which Synchronizes I/O for

Proper Automatic Test Pattern Generation for Multi-Phase Circuits

It is difficult for general purpose automatic test pattern generation (ATPG) software to recognize correctly the phase of the inputs or outputs of a multi-phase (more than one evaluation clock) circuit for which the test patterns are being generated. Providing stimulus to the inputs of the circuit in the wrong phase would ultimately end in incorrect circuit operation and therefore create inconsistencies between the circuit and the test model. This is because there is usually no way of telling the software what latch (phase) resides just outside the boundaries of the circuit other than including the latches themselves. Including the latches is inconvenient for the circuit designer because of the extra overhead of supporting a test-only model (with the extra I/O latches) and a real model (no I/O latches).

In multi-phase circuits, changes to Primary Inputs (PI's) must be made with regard to the phases of the various clocks, especially for dynamic circuits which depend on an evaluation clock following a precharge clock phase where only one change to the PI's is allowed during the evaluation phase. An example of the problems which occurred during test generation for an array macro which prompted this disclosure is now given. For this particular macro, ATPG produced test patterns or sequences of patterns of the form "sSMSPM" where s=stim the scannable latches, S=Stim the Primary Inputs, M=Measure the Primary Outputs, and P=Pulse the clock(s). The problem: after s (which ends with a clock pulse) the dynamic circuits are left in a precharged state and only one Stim_PI is allowed to be subsequently evaluated by the dynamic circuit without another Pulse. The second S in the sequence requires another evaluation but there has been no preceding clock pulse to precharge the circuit; stated another way, two successive Stim_PI's have occurred with no intervening (clock) precharge. This problem is applicable to a general situation. The corrected sequence should look like this: "sSMS'P'SPM" where the second S of the original has been replaced with the sub-sequence "S'P'S". Here S' conditions the PI's to generate the correct clocking when P' is applied, then S implements the original Stim_PI. Our original solution was to use this replacement scheme and replace each S with "S'P'S" to insure a precharge always preceded a Stim_PI. This is more replacement than is necessary but it is very difficult to replace specific S patterns. The problem with this solution is that each possible sequence needs to be pre-defined to the ATPG for it to replace the sequences. That is, simply replacing each S with "S'P'S" is not possible without explicitly enumerating each sequence that will be generated, since the ATPG replaces the entire sequence, not the sub-sequence.

A method for automatically including the necessary I/O latche...