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METHOD FOR THE DEFERRED MATERIALIZATION OF CONDITION CODE INFORMATION

IP.com Disclosure Number: IPCOM000014832D
Original Publication Date: 2000-Mar-01
Included in the Prior Art Database: 2003-Jun-20
Document File: 3 page(s) / 47K

Publishing Venue

IBM

Abstract

Disclosed is a translation approach to reduce the number of instructions which need to be executed by a binary translation system. More specifically, the approach is designed to allow accurate 100% system level binary translation to make use of control flow and live range anal- ysis while preserving complete accuracy in the presence of unpredictable exceptions in full system binary translation. To maintain a consistent architectural state, emulation and binary translation systems must compute all observable data values computed by an input program, even if these values may never be accessed subsequently. For many architectures, this information includes condition code values which may be implicitly set by all or most instructions of an architecture. (Exam ples of such architectures are IBM System/390, DEC VAX and Intel x86). This incurs computation overhead to compute unused data values. In addition, due to system-specific nature of condition code setting, significant work may have to be expended to compute the condition codes accurately on another system. While liveness information can be used to identify unused condition code computation, this information is necessarily incomplete for full system simulation. More particularly, such liveness analysis cannot detect control flow which may occur due to exception or trap oper- ations, e.g., due to page faults.

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  METHOD FOR THE DEFERRED MATERIALIZATION OF CONDITION CODE INFORMATION

    Disclosed is a translation approach to reduce the number of instructions which need to be executed by a binary translation system. More specifically, the approach is designed to allow accurate 100% system level binary translation to make use of control flow and live range anal- ysis while preserving complete accuracy in the presence of unpredictable exceptions in full system binary translation.

To maintain a consistent architectural state, emulation and binary translation systems must compute all observable data values computed by an input program, even if these values may never be accessed subsequently. For many architectures, this information includes condition code values which may be implicitly set by all or most instructions of an architecture. (Exam ples of such architectures are IBM System/390, DEC VAX and Intel x86).

This incurs computation overhead to compute unused data values. In addition, due to system-specific nature of condition code setting, significant work may have to be expended to compute the condition codes accurately on another system.

While liveness information can be used to identify unused condition code computation, this information is necessarily incomplete for full system simulation. More particularly, such liveness analysis cannot detect control flow which may occur due to exception or trap oper- ations, e.g., due to page faults.

Thus, while liveness information can be used to eliminate the computation of condition code information when problem state programs from one instruction set architecture to another
(e.g., the VEST and Wabi translators), such information cannot be readily used by full system simulation.

However, binary translators face a problem when encountering a potential exit from a trans- lation unit, and it is unknown whether the condition code will be used in the successor group. This is addressed by dynamic deferred condition code materialization, where instructions store the operands and the source values in some storage. The assumption is that executing instructions to store these values is cheaper than actually computing the correct condition codes [3].

The problem is somewhat different on an architecture designed to efficiently support binary translation from one or more source architectures to a target architecture. However, when performing full system simulation as described in [1][2], computations of dead condition codes cannot be suppressed. As a result, a significant number of condition code computations may be required in the generated code. These computations are usually useless, but required to maintain the accurate processor state in the case of exceptions.

The proposed method uses static information to perform deferred materialization of condition codes which are dead within a translation group but which may be required in the case of an exception (e.g., due to a page fault). Unlike dynamic deferred materi...