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Priority Scheme for allocating bus cycles to 1 of several simultaneous pipelines with input buffer FIFOs

IP.com Disclosure Number: IPCOM000014857D
Original Publication Date: 2002-Apr-06
Included in the Prior Art Database: 2003-Jun-20
Document File: 6 page(s) / 61K

Publishing Venue

IBM

Abstract

This invention allocates usage of a common interface bus to a shared memory to 1 of 4 pipelines based on the amount of available data in the input FIFOs of each pipeline. This allocation logic takes into account the available data in each FIFO, the availability of more data for each pipeline, the decodes that indicate whether each pipeline is active and whether an "End-of-Object" decode has been detected in the pipeline decompression logic.

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  Priority Scheme for allocating bus cycles to 1 of several simultaneous pipelines with input buffer FIFOs

This invention allocates usage of a common interface bus to a shared memory to 1 of 4 pipelines based on the amount of available data in the input FIFOs of each pipeline. This allocation logic takes into account the available data in each FIFO, the availability of more data for each pipeline, the decodes that indicate whether each pipeline is active and whether an "End-of-Object" decode has been detected in the pipeline decompression logic.

This allocation logic increases the priority for a pipeline as the pipeline nears a point where it will run empty and stop the printing process. This balances the data flow to each pipeline given that the compression ratio for each decompressor can vary widely. In addition, this scheme fetches a little data for each pipeline before trying to fill any of the FIFOs so that the time to start decompression is kept low.

Shown below is the Verilog that implements most of this function. The decodes of the FIFO's word count register aren't shown. The FIFO decodes are such signals as OBJ1_LW_CNT_000_007. This signal says that the OBJ1 decompressor associated FIFO has 0-7 words of data not yet loaded into the decompressor. Decodes are generated for 0-7 words, 0-31 words, 0-63 words & 0-127 words as well as a signal that indicates that there is at least an 8 word hole in the FIFO that data can be loaded into. In this example, 8 words is the bus burst length for 1 burst. The "hole" signal is called OBJ1_LW_FF_BURST_OF_8_OK for decompressor OBJ1. This signal is a decode of 0-248 words used out of a 256 word maximum count. There are data ready signals (example LW3_DRDY_N) for each of 8 object storage areas for each of 2 buses -- Linework (LW) and Linework Control (LWC). These signals allow the FIFO loading priority logic to constantly monitor the availability of data for each object for both data types (LW & LWC).

The following logic exists (separately) for several pipelines and decompressors.

/***************************************************/

/* Line Work Data bus state machine */ /***************************************************/

/***************************************************/

/* Latching up the data ready signals */

1

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/* These signals come from the memory and indicate */ /* whether there is data */ /* available. LW3_DRDY_N = 0 means there is data */ /* for interface ID = 011 */ /***************************************************/

always @ (posedge CLK_16 or negedge LW_RST_N) if (!LW_RST_N) begin

LW0_DRDY <= 1'b0;

LW1_DRDY <= 1'b0;

LW2_DRDY <= 1'b0;

LW3_DRDY <= 1'b0;

LW4_DRDY <= 1'b0;

LW5_DRDY <= 1'b0;

LW6_DRDY <= 1'b0;

LW7_DRDY <= 1'b0;

end else

begin

LW0_DRDY <= !LW0_DRDY_N;

LW1_DRDY <= !LW1_DRDY_N;

LW2_DRDY <= !LW2_DRDY_N;

LW3_DRDY <= !LW3_DRDY_N;

LW4_DRDY <= !LW4_DRDY_N;

LW5_DRDY <= !LW5_DRDY_N;

LW6_DRDY <= !LW6_DRDY_N;

LW7_DRDY <= !LW7_DRDY_N;

end

/*************************...