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Manufacturing process to fabricate co-planar multi-level printed circuit boards

IP.com Disclosure Number: IPCOM000014863D
Original Publication Date: 2002-Oct-18
Included in the Prior Art Database: 2003-Jun-20
Document File: 9 page(s) / 155K

Publishing Venue

IBM

Abstract

A manufacturing process for insuring co-planarity of epoxy printed circuit boards fabricated with more than one level on a side having different planar surface dimensions is described. Individual layers of printed circuit board material (comprised of differing circuit layout configurations,) are integrally-laminated with a printed circuit board "core" (main-body circuit board,) to create an assembly having one or more mechanical "bosses" that project from the main printed circuit board surface. (These bosses are to be further referred to as "pedestals.")

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Manufacturing process to fabricate co-planar multi-level printed circuit boards

       A manufacturing process for insuring co-planarity of epoxy printed circuit boards fabricated with more than one level on a side having different planar surface dimensions is described. Individual layers of printed circuit board material (comprised of differing circuit layout configurations,) are integrally-laminated with a printed circuit board "core" (main-body circuit board,) to create an assembly having one or more mechanical "bosses" that project from the main printed circuit board surface. (These bosses are to be further referred to as "pedestals.")

       The necessity of printed circuit board pedestals are to;- (1.) allow for internal circuitry and surface contact pads to make electrical connections to test probe contactors with Z-height restrictions, (2.) allow vertical clearance for electronic components to be soldered about the perimeter of the pedestal, thereby preventing mechanical interference to surface-mating probe hardware, & (3.) compensate for thickness variations between interchangeable circuit boards to maintain dimensional compatibility between them without requiring the use of external shims for thickness compensation for each board assembly when physically installed in compatible mounting frame hardware.

       This eliminates typical non-co-planarity problems observed in existing fabrications of a printed circuit board assembly having smaller pedestals laminated to either the top and/or bottom surfaces of a physically-larger main-body printed circuit board. A unique manufacturing process also allows for the location of multiple pedestals anywhere on the larger main-body printed circuit board's top and/or bottom surfaces. (Present technology board fabrication techniques do not allow for this construction.)

       The problem of non-co-planarity of adjacent parallel surfaces within multi-level printed circuit board assemblies is solved by allowing a board to be fabricated with a uniform laminating compression across all parallel surfaces, thus significantly-reducing problems with board warpage. (An attempt to use a conventional laminating process for fabricating pedestal printed circuit boards results in significant potential of board warpage from a difficulty to control the uniformity of laminating compression.)

       Board thickness and/or height variations are minimised while still maintaining an integral tight-tolerance co-planarity condition between all surfaces.

       The actual pedestal printed circuit board fabrication process may slightly vary depending upon the physical board design, pedestal location(s), and wiring requirements. Variations of this assembly process can be made to create multiple independent pedestals anywhere on the board surface, on one side or both sides simultaneously, & all surfaces co-planar within a tight dimensional tolerance to each other. The following paragraphs explain the basics of how a "typical" pedestal printed circuit bo...