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A Conflict-Free Multi-Output Port FIFO Memory Composed of Memory Elements Slower than the Total Line Rate

IP.com Disclosure Number: IPCOM000014884D
Original Publication Date: 2001-Apr-15
Included in the Prior Art Database: 2003-Jun-20
Document File: 3 page(s) / 55K

Publishing Venue

IBM

Abstract

A memory system is disclosed which has one write port and several read ports. It emulates a FIFO with the restriction that the read ports are not permitted to stop reading. Such a memory is useful in applications where packets destined for a particular output port (read-port) may arrive much more quickly than that output can read them. Therefore they must be stored temporarily. The particular feature of this memory system is that it consists of several memory elements, each of which is slower than the required data throughput of the system, but which are combined in such a way as to make a system with the required (much higher) aggregate throughput. The memory system comprises several memory elements, each of which is slower than the required data throughput of the system, but which are combined in such a way as to make a system with the required (much higher) aggregate throughput. Time is divided into slots of fixed duration. During each time slot a unit of data of fixed width (a cell) may arrive at the write (input) port. Each cell is accompanied by the number of the read (output) port to which it will be sent. During the same time slot, one of the output ports reads a cell from the data-store. The outputs are serviced in round-robin fashion.

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  A Conflict-Free Multi-Output Port FIFO Memory Composed of Memory Elements Slower than the Total Line Rate

A memory system is disclosed which has one write port and several read ports.

It emulates a FIFO with the restriction that the read ports are not permitted to stop reading. Such a memory is useful in applications where packets destined for a particular output port (read-port) may arrive much more quickly than that output can read them. Therefore they must be stored temporarily.

The particular feature of this memory system is that it consists of several memory elements, each of which is slower than the required data throughput of the system, but which are combined in such a way as to make a system with the required (much higher) aggregate throughput.

The memory system comprises several memory elements, each of which is slower than the required data throughput of the system, but which are combined in such a way as to make a system with the required (much higher) aggregate throughput. Time is divided into slots of fixed duration. During each time slot a unit of data of fixed width (a cell) may arrive at the write (input) port. Each cell is accompanied by the number of the read (output) port to which it will be sent. During the same time slot, one of the output ports reads a cell from the data-store. The outputs are serviced in round-robin fashion.

The system comprises 4 main sub-systems:

1) A data-store composed of "layers" (NLAY in number)

2) A set of output ports (NQ in number)

3) The output controller

4) The input controller

5) a circular counter which acts as a clock.

Each layer of the data-store emulates a memory with the same number of output queues as there are output ports. For a given layer number k there is:

1) a memory element called ME.k, each location of which stores a data cell.

2) a control store which stores the chains of pointers which implement the linked lists for
a) the free memory locations and b) the memory locations used by each of the output queues. For the layer k this is called LL.k.

3) an array of bits where each bit corresponds to a time slot, and where a 1 denotes that that time slot is "occupied" (e.g. by a read operation on that layer) or free. This array is circular (like a clock). For layer k this is called FO.k.

4) a counter NOCANWRITE.k which can be set to an initial value and which decrements towards 0 in each time slot. This counter is set to the value MEMSLOTS each time a

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cell is written to this layer. MEMSLOTS is that number of time slots occupied by a write operation on the memory element.

5) A single bit FULL.k denoting if that layer is full or not.

Each output port consists of a number of elements. For a given output port number q:

1) There is a multiplexer which selects the layer from which the data cell is to be read.

2) There is a register which contains the "departure time" of the next cell to be written to this output. This register is updated each time a cell for this...