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A DSP architecture for multi threaded applications

IP.com Disclosure Number: IPCOM000014886D
Original Publication Date: 2001-Feb-20
Included in the Prior Art Database: 2003-Jun-20
Document File: 8 page(s) / 62K

Publishing Venue

IBM

Abstract

The following propose a novel solution at the architectural and system level for multi channel real-time applications. Applications such as modem banks (like V.90), VoIP gateways (audio coders), wireless base station (Like GSM), and even switches can benefit from this architecture by providing a much better cost/performance ratio. The document outlines a novel architecture for a DSP (and even other purpose CPUs) that can allow the use of small and inexpensive DRAM in place of fast, large and expensive SRAM. The new architecture is especially suitable for multi unrelated threaded applications, nevertheless it can be utilized also for general tasks. The new DSP does not include a cache architecture and performs all the tasks in a deterministic manner. The new architecture can be applied to many existing cores with a small investment and almost no changes are required to existing legacy code. It may utilize the IBM embedded DRAM solution. The advantages of this architecture can provide IBM with the leading edge that is needed in order to play a significant role in the DSP market. Content · Introduction

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A DSP architecture for multi threaded applications

  The following propose a novel solution at the architectural and system level for multi channel real-time applications. Applications such as modem banks (like V.90), VoIP gateways (audio coders), wireless base station (Like GSM), and even switches can benefit from this architecture by providing a much better cost/performance ratio. The document outlines a novel architecture for a DSP (and even other purpose CPUs) that can allow the use of small and inexpensive DRAM in place of fast, large and expensive SRAM.

The new architecture is especially suitable for multi unrelated threaded applications, nevertheless it can be utilized also for general tasks. The new DSP does not include a cache architecture and performs all the tasks in a deterministic manner. The new architecture can be applied to many existing cores with a small investment and almost no changes are required to existing legacy code. It may utilize the IBM embedded DRAM solution. The advantages of this architecture can provide IBM with the leading edge that is needed in order to play a significant role in the DSP market.

Content

· Introduction
· A problem example
· Architecture description
· Comparison with other architectures
· Utilization by different application
· Summary Introduction Many computers in the industry are being used to process many unrelated but similar tasks at the same time. A few examples would be:
1. A switch that moves IP packets from one network to another
2. A DSP that runs several modems in order to provides the communication interface for Internet access.
3. A server CPU that runs several unrelated tasks like DB accessing service. In all of these cases a very fast CPU is utilized in order to provide the needed service in a timely manner. Due to such applications the CPU speed has been increased dramatically during the last years but the development of matching memories has been much slower. Supporting many channels (or services) at the same time leads to larger memories that must keep up with the CPU speed. These facts caused a larger and larger gap between the CPU speed and the speed of the available common memory. There are two main memory alternatives DRAM and SRAM, the first is slow and cheaper the second is fast and expansive. An SRAM memory that keeps up with the CPU speed is very expansive, a fact that directly affects a solution price. The footprint ratio between a DRAM and SRAM is about 1:10 respectively. This fact does not allow in most of the cases to use large SRAMs. Note that most DSPs require one cycle access time for efficiency reasons. Various memory architectures has been devised in order to solve this problem. In almost all cases a cache architecture of several layers has been developed in which the fastest memory that runs at the CPU speed is relatively small. Most PCs are offered

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with two SRAM cache layers in order to bridge the processor/memory performance gap. That...