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Small Carry Delay Adder by Input Selection

IP.com Disclosure Number: IPCOM000014888D
Original Publication Date: 2000-Mar-01
Included in the Prior Art Database: 2003-Jun-20
Document File: 4 page(s) / 73K

Publishing Venue

IBM

Abstract

Disclosed is a method to minimize carry delay of adder by optimizing adder's component using its input value.

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Small Carry Delay Adder by Input Selection

Disclosed is a method to minimize carry delay of adder by
optimizing adder's component using its input value.

This method also makes the adder's hardware much simpler.

According to this method, adder circuit constitution is different
depend on its input value. The constitution is determined so that
its carry line delay is minimized. The basic idea of this method
is to cut down adder into 1 bit pieces and replace each bit adder
with a optimized 1 bit half adder.

Figure 1 shows the optimized 1 bit half adder's components
proposed in this method. There are four different types of
adders, that is, HA1e, HA1o, HA0e, and HA0o. The distinctions of
these four adders are their input value (1 or 0) and their
location (even bit or odd bit). These adder's carry line consists
of only one NAND gate or one NOR gate. Thus the carry line delay
per 1 bit is the average of one stage NAND and one stage NOR gate
transfer delay. This makes carry line delay pretty short.

Figure 2 shows the circuit of 6 bit half adder.
This adder's delay line contains four NAND gates and two NOR
gates. The inverting delay of each odd bit input is not critical
because inverted value of each odd bit input settles before carry
in (cin bar) of each adder settles. Further, NAND and NOR circuit
is the simplest of all the multi-input gate, then total area
of the adder is very small.

As for full adder, it can consist of two kinds of half adder
by output multiplexing. Figure 3 shows this...