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Automatic Method for Verifying NDR and Simulation Models

IP.com Disclosure Number: IPCOM000014941D
Original Publication Date: 2001-Oct-20
Included in the Prior Art Database: 2003-Jun-20
Document File: 8 page(s) / 141K

Publishing Venue

IBM

Abstract

Automatic method for verifying NDR and simulation models

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Automatic Method for Verifying NDR and Simulation Models

Automatic method for verifying NDR and simulation models

ABSTRACT

This paper describes the methods of checking New Delay Rule (NDR) and simulation models. NDR verification includes the generation of Standard Delay Format (SDF) file from NDR and checking the correctness of all entries in the file. Simulation model checking includes checking the functionality of Verilog and VITAL books, io path propagation delay back annotation and timing checks back annotation. PERL ( Practical Extraction and Report Language ) script is used to develop this method. This method is applied on library CMOS7SFLPGA which is developed in IBM YASU, Japan. Various bugs have been found in NDR and models.

1. Introduction

In the development phase of LSI, New Delay Rule (NDR) is used for timing analysis. These NDR rules are unique to each technology. So after the development of NDR for a particular technology, verification is very important. Manual verification is cumbersome, time consuming and error prone. Other important aspects are functional and timing verifications of LSI after logic synthesis. This is done by using the Gate level net list obtained after logic synthesis targeted to a particular technology. Gate level netlist consists of many technology dependent books. To represent these books Verilog and VITAL models are being used. So before releasing these models correct functionality and timing checks have to be ensured. Currently there are no tools available to fulfill these requirements. In this paper we introduce an automatic method for testing NDR. Also we describe automatic methods for testing the functionality, IOPATH delay annotation and Timing Checks verification of Verilog and VITAL models of technology dependent books.

2. NDR Checking

NDR checking is done with the help of SDF files which is generated from NDR.In other words NDR checking means checking the correctness of SDF file. SDF file consists of two parts : 1) Interconnect delays between the components in the design,
2) IOPATH(Input to Output path) delays and Timing Checks for various components. IOPATH delays and Timing Checks for various books are generated in the SDF file according to the NDR for respective books. In the case of Non-Latch Cells the NDR means only IOPATH delays for the cells. i.e., the key factors which have to be taken into consideration are,
1) All the valid IOPATHs corresponding to the cell are present in NDR.
2) The delay value corresponding to IOPATH is a non-negative value.
3) All non-valid paths are not present in NDR. The following diagram shows the various stages of NDR checking.

1

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Figure 1: NDR checking.

For e.g., in the case of PSHRDI1 cell, the truth table is given below.

Table 1 : Truth table of PSHRDI1 cell.

Inputs Outputs

TE D DI Z ZDI 0 X X DI 1
1 X X D DI

In this all valid IOPATHs are


1) DI to Z
2) D to Z
3) DI to ZDI
4) TE to ZDI
5) posedge TE to Z
6) negedge TE to Z

And non-valid IOPATH...