Browse Prior Art Database

Method and Apparatus for Temporally Shared Access to a Common JTAG Interface

IP.com Disclosure Number: IPCOM000014976D
Original Publication Date: 2001-Sep-13
Included in the Prior Art Database: 2003-Jun-20
Document File: 3 page(s) / 43K

Publishing Venue

IBM

Abstract

Disclosed is an invention which allows parallel independent JTAG (IEEE 1149.1) instruction streams to overlap using a single physical interface. Local interfaces include both JTAG (IEEE 1149.1) and IIC (Integrated Circuit Interconnect, Phillips Corp, public domain). The interfaces merge on chip in a common JTAG bus. This bus was not designed to accommodate temporally concurrent transfer streams. When such an overlap occurs, the transfer is garbled, leading to incorrect data exchange and/or incorrect future operation. Proper operation may be insured via a software semaphore "lock" which allows only one interface to be active at a time. This invention overcomes this limitation in most cases by allowing parallel independent instruction streams to interleave. Software overhead is reduced and interface performance enhanced.

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  Method and Apparatus for Temporally Shared Access to a Common JTAG Interface

    Disclosed is an invention which allows parallel independent JTAG (IEEE 1149.1) instruction streams to overlap using a single physical interface. Local interfaces include both JTAG (IEEE 1149.1) and IIC (Integrated Circuit Interconnect, Phillips Corp, public domain). The interfaces merge on chip in a common JTAG bus. This bus was not designed to accommodate temporally concurrent transfer streams. When such an overlap occurs, the transfer is garbled, leading to incorrect data exchange and/or incorrect future operation. Proper operation may be insured via a software semaphore "lock" which allows only one interface to be active at a time. This invention overcomes this limitation in most cases by allowing parallel independent instruction streams to interleave. Software overhead is reduced and interface performance enhanced.

  JTAG transfers do not have adequate provision allowing them to be temporally delayed. Furthermore, the instruction/data transfer sequence is "atomic" while in the Shift-IR or Shift-DR states. IIC transfers may be paced by the slave device following the acknowledge bit timing. This opens a window for buffering one of the on-chip JTAG data streams (native JTAG vs IIC translation) while in non-shift states (see Figure 1). Some of the other JTAG/TAP controller states create buffering problems as well (see Figure 2), dependant upon the active instruction in the IR (JTAG Instruction Register). The IIC-to-JTAG translated data stream is prevented from initiating...