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Method and Apparatus for Dynamically Injecting Diagnostic Errors in Digital Systems

IP.com Disclosure Number: IPCOM000015103D
Original Publication Date: 2002-Jan-27
Included in the Prior Art Database: 2003-Jun-20
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Abstract

Disclosed is method and system for dynamically injecting errors in digital systems. The disclosed method and system enables comprehensive testing of the error handling capabilities of both hardware and software during the development and validation of digital system designs. An existing method used for this task utilizes a serial interface such as IEEE 1149.1 (a.k.a. JTAG) to write a special hardware register which is used to identify a particular error to inject. Hardware decodes the contents of the register and then typically injects the selected error by logically forcing specific signals. The effect is to inject or force an error for the duration that the register remains unchanged. The existing system is very well suited to injecting static or semi-permanent errors, but is inherently limited by the slowness of the JTAG interface and the associated software when it comes to injecting dynamic errors. In the real world many types of errors are dynamic in nature and the ability to validate the error handling design of a digital system in a flexible and dynamic manner is a very desirable capability. To overcome the limitations of the existing system and provide for programmable dynamic error injection, a method and apparatus comprised primarily of control registers and a pulse generating circuit is presented. The apparatus for this new method is comprised of a set of registers, a decoder, a pulse generator, and logic gates. The registers can be initialized or written by any means, but a preferred implementation is to use an IEEE 1149.1 interface driven by an external host or test tool. All the registers are not required, but are included in a preferred implementation.

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  Method and Apparatus for Dynamically Injecting Diagnostic Errors in Digital Systems

   Disclosed is method and system for dynamically injecting errors in digital systems. The disclosed method and system enables comprehensive testing of the error handling capabilities of both hardware and software during the development and validation of digital system designs.

An existing method used for this task utilizes a serial interface such as IEEE 1149.1 (a.k.a. - JTAG) to write a special hardware register which is used to identify a particular error to inject. Hardware decodes the contents of the register and then typically injects the selected error by logically forcing specific signals. The effect is to inject or force an error for the duration that the register remains unchanged.

The existing system is very well suited to injecting static or semi-permanent errors, but is inherently limited by the slowness of the JTAG interface and the associated software when it comes to injecting dynamic errors. In the real world many types of errors are dynamic in nature and the ability to validate the error handling design of a digital system in a flexible and dynamic manner is a very desirable capability. To overcome the limitations of the existing system and provide for programmable dynamic error injection, a method and apparatus comprised primarily of control registers and a pulse generating circuit is presented.

The apparatus for this new method is comprised of a set of registers,...