Browse Prior Art Database

PLL Unlock Detector

IP.com Disclosure Number: IPCOM000015168D
Original Publication Date: 2002-Apr-11
Included in the Prior Art Database: 2003-Jun-20
Document File: 6 page(s) / 107K

Publishing Venue

IBM

Abstract

Disclosed is a method to detect uniform locking condition of the PLL for any divisor values of the PLL dividers. This method generates unlock signal of the PLL with "up" output, "down" output of phase frequency detector, divided reference clock (Ref. Clock) and divided VCO Clock. An unlock detector (ULD) is proposed to implement this method. This ULS indicates the timing when PLL is locked to a target frequency and phase. This ULD detects the lock condition in a same accuracy independently of divisor values. Figure 1 shows the circuit of the PLL which uses the proposed ULD. 1 According to this method, "Unlock" signal of the PLL is generated by using "up" output, "down" output of a phase frequency detector, divided reference clock (Ref. Clock) and divided VCO clock.

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PLL Unlock Detector

Disclosed is a method to detect uniform locking condition of the PLL for any divisor values of the PLL dividers. This method generates unlock signal of the PLL with "up" output, "down" output of phase frequency detector, divided reference clock (Ref. Clock) and divided VCO Clock.

An unlock detector (ULD) is proposed to implement this method. This ULS indicates the timing when PLL is locked to a target frequency and phase. This ULD detects the lock condition in a same accuracy independently of divisor values. Figure 1 shows the circuit of the PLL which uses the proposed ULD.

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According to this method, "Unlock" signal of the PLL is generated by using "up" output, "down" output of a phase frequency detector, divided reference clock (Ref. Clock) and divided VCO clock.

Figure 2 shows the block diagram of the proposed ULD circuit.

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There are two programmable clock cycle delays (PCCD1 and PCCD2) in this circuit. The programmable clock cycles of the PCCD1 and that of PCCD2 are proportional to the value N (the divisor of divider DIV N) and D (the divisor of divider DIV D), respectively. The PCCDs receive the output of the pulse generators (PGs) which

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make pulses with a certain width tPG from the outputs of DIV N and DIV D, respectively. A programmable timer that works with Ref. Clock and several gates together with these PCCDs compose the ULD.

Figure 3 shows the operation timing of the ULD. At the beginning, the "Unlock" signal is set to high by initialization circuit.

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At this moment, the programmable counter is reset and starts to count up "Ref. Clock" one by one. A reset signal for programmable timer is generated if there is an overlap period between the PCCD1's output node A (or the PCCD2's output node B) and the up (or down) signal. During this overlap period, node C or node D is high. The programmable timer is reset when node C or node D is high. The unlock signal is kept being activated until the programmable timer reaches a programmed value. In other words,

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the unlock signal is inactive if all the "up" pulses are narrower than tD1 (the delay of the PCCD1) and all the "down" pulses are narrower than tD2 (the delay of the PCCD2). The delay of the PCCD1 is determined with clock cycle of the "Ref. clock", N (the driver of DIV N) and 1/k. The delay of the PCCD2 is determined with clock cycle of "VCO Clock", D (the divisor of DIV D) and 1/k. The proportional constant 1/k i...