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Method of sequential match-address output in content addressable memory

IP.com Disclosure Number: IPCOM000015170D
Original Publication Date: 2002-Apr-11
Included in the Prior Art Database: 2003-Jun-20
Document File: 4 page(s) / 79K

Publishing Venue

IBM

Abstract

Disclosed is a method of sequential match-address output in content addressable memory (CAM) which has address encoder and word-match latch when plural address are matched by search operation. The sequence of output address is correspond to the predefined priority in address encoder. CAM outputs an address match signal and address in which word has the contents matched with search data when search operation is performed. When search data matched with the contents at plural address, CAM outputs one address according to the priority predefined by an address encoder. Figure 1 shows a block diagram of a conventional CAM. An Address Decoder receives address input, address_in, and decodes one of the word address in a CAM Cell Array. The CAM Cell Array stores data at each word address. A Valid cell contains cells which hold flags corresponding to each word address of the CAM Cell Array. It defines the searchable address. A Word-match Detector detects whether input data match the contents in the CAM Cell Array at every word address. A Word-match Latch holds the results from the Word-match Detector. An Address Encoder outputs match-address based on the predefined priority with data from the Word-match Latch. It also outputs address match signal, address_match. A Controller controls CAM operation with command signal. A Bit Switch connects Bit Line and Data Line. A Data Write and Search Driver works for write and search operation. A Data Read Sense Amplifier senses read data on Data Line for read operation. In a conventional CAM it needs two cycles to output one match-address during outputting plural match-address sequentially. There are two methods to achieve this. One is resetting the Valid Cell by write operation at address which is currently output. then doing search operation. The other is writing different data from searching data at address which is currently output. then doing search operation. Both methods need to remember at which address is reset or written and to write back original data there.

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Method of sequential match-address output in content addressable memory

    Disclosed is a method of sequential match-address output in content addressable memory (CAM) which has address encoder and word-match latch when plural address are matched by search operation. The sequence of output address is correspond to the predefined priority in address encoder.

    CAM outputs an address match signal and address in which word has the contents matched with search data when search operation is performed. When search data matched with the contents at plural address, CAM outputs one address according to the priority predefined by an address encoder.

    Figure 1 shows a block diagram of a conventional CAM. An Address Decoder receives address input, address_in, and decodes one of the word address in a CAM Cell Array. The CAM Cell Array stores data at each word address. A Valid cell contains cells which hold flags corresponding to each word address of the CAM Cell Array. It defines the searchable address. A Word-match Detector detects whether input data match the contents in the CAM Cell Array at every word address. A Word-match Latch holds the results from the Word-match Detector. An Address Encoder outputs match-address based on the predefined priority with data from the Word-match Latch. It also outputs address match signal, address_match. A Controller controls CAM operation with command signal. A Bit Switch connects Bit Line and Data Line. A Data Write and Search Driver works for write and search operation. A Data Read Sense Amplifier senses read data on Data Line for read operation.

    In a conventional CAM it needs two cycles to output one match-address during outputting plural match-address sequentially. There are two methods to achieve this. One is resetting the Valid Cell by write operation at address which is currently output. then doing search operation. The other is writing different data from searching data at address which is currently output. then doing search operation. Both methods need to remember at which address is reset or written and to write back original data there.

    As mentioned above, the conventional CAM takes (3n - 2) cycles to output all the matched address when a number of word-match is n in one search operation.

      Search n cycles Reset or write (n - 1) cycles Write back (n - 1) cycles
Total (3n - 2) cycles Figure 2 shows a waveform of the conventional CAM. When clock goes low from high, a CAM starts memory cycle by fetching commands (write or search), input address (address_in), and search data (omitted in Figure 2). When clock goes high from low, the Word-match Latch fetches the result of the Word-match Detector. The CAM does search operation and outputs address A as a match-address at T1. This address is used as the input address for write operation at T2. The CAM resets the Valid Cell or writes different data from search data used at T1. At T3, address A is no longer a search target by write operation at T2. Therefore the CA...