Browse Prior Art Database

New Idd screening method

IP.com Disclosure Number: IPCOM000015171D
Original Publication Date: 2002-Apr-11
Included in the Prior Art Database: 2003-Jun-20
Document File: 2 page(s) / 1M

Publishing Venue

IBM

Abstract

Disclosed is a screening method for testing semiconductor devices by comparing standby current (Idd) and the ideal relationship between Idd and speed obtained from good devices, which is named Statistical Variable Idd Screening (SVIS). It enables to improve the sensitivity of Idd screening as defect detection test by dynamic current limit changing on each device.

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New Idd screening method

        Disclosed is a screening method for testing semiconductor devices by comparing standby current (Idd) and the ideal relationship between Idd and speed obtained from good devices, which is named Statistical Variable Idd Screening (SVIS). It enables to improve the sensitivity of Idd screening as defect detection test by dynamic current limit changing on each device.

     Fig.1 shows schematic chart to understand current problem in Idd screening. Idd current distributions vary by their performance speed and upper limit is determined by highest speed case. Therefore even if sample distribution is not on standard distribution like sample.1, maverick chips can not be screened out. These maverick chips have high possibility to have some defect in it. This invention focus on the relationship between Idd and speed and adequate Idd upper limit is set on a real time, basis based on obtained speed data and known Idd-speed relationship.

The steps of SVIS are as follows.
(1) In order to obtain the relationship between Idd current and speed data, data should be collected from the initial samples of product. Then the formula of their relationship are derived by data fitting. (Fig.2)
(2) Tolerance is statically calculated as SVIS fail chip percentage become 3 sigma. After the addition of this tolerance into fitting curve, Idd upper limit equation is determined as a function of speed.
(3) Wafer final test is performed on each device in a wafer, and then SVIS pass/...