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CMOS On-Chip Oscillator Circuit with Programmable Hysteresis

IP.com Disclosure Number: IPCOM000015176D
Original Publication Date: 2002-Apr-11
Included in the Prior Art Database: 2003-Jun-20
Document File: 2 page(s) / 117K

Publishing Venue

IBM

Abstract

Disclosed is a circuit for CMOS On-chip oscillator which makes the hysteresis of receiver adjustable with control signals. This new type of circuit chooses the appropriate hysteresis width complying with the application and the condition of printed circuit board so that it can highten the noise tolerance and supply the stable clock to the internal circuits.

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CMOS On-Chip Oscillator Circuit with Programmable Hysteresis

Disclosed is a circuit for CMOS On-chip oscillator which makes the hysteresis of receiver adjustable with

control signals. This new type of circuit chooses the appropriate hysteresis width complying with the

application and the condition of printed circuit board so that it can highten the noise tolerance and supply the

stable clock to the internal circuits.

The circuit basically consists of a conventional Pierce oscillator and the new type of Schmitt Trigger receiver which has two input signals, HYST1 and HYST2, to control the hysteresis width to be immune to noise and supply the high quality clock into the internal circuits. In Fig.A, the Pierce oscillator is formed with the INV1 and the external feedback resistor between PAD and PAD1 and the additional capacitors on PAD and PAD1. Also, the circuits coming up after INV2 is the receiver with the controllable hysteresis. In this schematic, the PFETs, P1, P2 and the NFETs, N1, N2 make it possible to create four kinds of hysteresis width with the HYST1 and HYST2. The following table shows the hysteresis width varied in compliance with states of HYST1 and HYST2, when the device size of the PFET P1 is assumed to be bigger than that of P2 and also, N1 is bigger than N2.

HYST1HYST2 HYSTERESIS

WIDTH

ยทยท Hyst_curve.pdf

File

 0 0 NO Fig. 1 0 1 SMALL Fig. 2 1 0 MIDDLE Fig. 3 1 1 LARGE Fig. 4 The hysteresis curves are shown in Fig.1 to Fig.4. In the simulation, the assumption of device size is as fo...