Browse Prior Art Database

C-clock Sharing

IP.com Disclosure Number: IPCOM000015258D
Original Publication Date: 2002-Apr-11
Included in the Prior Art Database: 2003-Jun-20
Document File: 1 page(s) / 76K

Publishing Venue

IBM

Abstract

In order to prevent "racing" in LSSD test, usually multiple CCLOCK is required and as such, multiple physical pins are occupied by LSSD CCLOCK. Usually 3 to 5 cclocks are used in actual ASIC. This invention prevents racing condition in LSSD test without requiring multiple cclock. Below chart shows the circuit of this invention. Only one of the outputs of the decoder(indicated by A,B,C in the below chart) is active at a time so that only one cclock can be active at the same time, thus prevents the racing condition at LSSD test.

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C-clock Sharing

    In order to prevent "racing" in LSSD test, usually multiple CCLOCK is required and as such, multiple physical pins are occupied by LSSD CCLOCK. Usually 3 to 5 cclocks are used in actual ASIC. This invention prevents racing condition in LSSD test without requiring multiple cclock. Below chart shows the circuit of this invention. Only one of the outputs of the decoder(indicated by A,B,C in the below chart) is active at a time so that only one cclock can be active at the same time, thus prevents the racing condition at LSSD test.

A

I

CCLK1

CCLK2

B

A

B

C

A

I

B

CCLK3

D ecoder

Scan O nly Latch

CCLO CK

In the case that the CCLOCK is shared with functional signal, the below circuit can be used.

A

I

CE1_C1

CE1_C2

CE1_C3

U sed as a Function

B

A

I

B

D ecoder circuit

A

B

C

FunctionS ig

CE0_TE

A

I

0

1 S

B

1

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