Browse Prior Art Database

CCLOCK Generator in Logic BIST

IP.com Disclosure Number: IPCOM000015259D
Original Publication Date: 2002-Apr-11
Included in the Prior Art Database: 2003-Jun-20
Document File: 1 page(s) / 72K

Publishing Venue

IBM

Abstract

During Logicbist test in lssd latches, it is necessary to provide exclusive relation to some C-clocks and Set/reset signals. Otherwise they can not be tested regardless that they are important signals.·Look at the drawing below. Scanonly latchs in left side (Scanonly_i, i=1,...,n) are loaded random value(This can be prpg or any flops of bist channel) at every bist cycle. Decoder is placed in the downstream of the latches. The decoder's outputs are designed so that decoded signals are exclusively turned on. This is necessary to have mutually exclusive clocks/Set/Reset signals. For instance if Dec_1(Blue line) takes '1', Dec_2, Dec_k-1, Dec_k signals take '0'. This mutually exclusive circuit privide a way to test set/reset pins and c-clocks which should not be turned on at test time. Also, each decoded signals could be weighted.

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CCLOCK Generator in Logic BIST

    During Logicbist test in lssd latches, it is necessary to provide exclusive relation to some C-clocks and Set/reset signals. Otherwise they can not be tested regardless that they are important signals.·Look at the drawing below. Scanonly latchs in left side (Scanonly_i, i=1,...,n) are loaded random value(This can be prpg or any flops of bist channel) at every bist cycle. Decoder is placed in the downstream of the latches. The decoder's outputs are designed so that decoded signals are exclusively turned on. This is necessary to have mutually exclusive clocks/Set/Reset signals. For instance if Dec_1(Blue line) takes '1', Dec_2, Dec_k-1, Dec_k signals take '0'. This mutually exclusive circuit privide a way to test set/reset pins and c-clocks which should not be turned on at test time. Also, each decoded signals could be weighted.

Din Cclk Sin Aclk

Din Cclk Sin Aclk Reset Set

C clk implementation with this invention

Clock generation for LogicBist

Control

Signals

Other test clocks for logic bist

CLKG

Source of test C clk

N ins -> K outs decode

(K =< N**2-1)

LogicBist osc

and_1

and_2Splt-1

and_k-1

and_k

Dec_1

Dec_2

Splt-2

L1L2_2

L1L2_3

L1L2_1

testc osc c

testc osc c

Scanonly_1

Scanonly_2

Scanonly_3

Scanonly_4

Scanonly_n

Cgate_1 Cgate_2 Cgate_3 Cgate_4

Cgate_n

Din Cclk Sin Aclk


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or_k-1

or_k

Dec_k-1

Dec_k

function c1 function set function reset function c2 clk

1

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