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SYNCHRONIZATION OF SERIAL DATA COMMUNICATION

IP.com Disclosure Number: IPCOM000015306D
Original Publication Date: 2002-Jul-01
Included in the Prior Art Database: 2003-Jun-20
Document File: 3 page(s) / 50K

Publishing Venue

IBM

Abstract

Disclosed is a method to synchronize a serial data link while using a multi Level communication system. The basic idea is to use special symbol, which is not '1' or '0', in order to indicate the 'sync' position, which periodicaly separates between data groups. Beside the indication of groups boundaries, the sync is an elegant way to synchronize the Receiver, with or without PLL (Phase Locked Loop). In ordinary binary serial links there is no sync bit possibility because it can't be distinguished from the data. As a result, the clock must be embedded with the data in some other code: Manchester, 8/10, 64/66... etc. None of those embedded codes has the feature of dividing the data into equal groups (bytes, words, etc.). However, in multi Level system, the sync bit can easily be implemented by another Level (see Fig. 1). Thus yielding a straight forward method to separate between data groups. sync bit sync bit data

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SYNCHRONIZATION OF SERIAL DATA COMMUNICATION

Disclosed is a method to synchronize a serial data link while using a multi Level communication system. The basic idea is to use special symbol, which is not '1' or '0', in order to indicate the 'sync' position, which periodicaly separates between data groups. Beside the indication of groups boundaries, the sync is an elegant way to synchronize the Receiver, with or without PLL (Phase Locked Loop). In ordinary binary serial links there is no sync bit possibility because it can't be distinguished from the data. As a result, the clock must be embedded with the data in some other code: Manchester, 8/10, 64/66... etc. None of those embedded codes has the feature of dividing the data into equal groups (bytes, words, etc.). However, in multi Level system, the sync bit can easily be implemented by another Level (see Fig. 1). Thus yielding a straight forward method to separate between data groups.

sync bit

sync bit

data

s

s

Tx

Rx

                          Fig. 1 : Serial link synchronization The simple group boundaries is not the only advantage of the multi Level sync symbol. It is also very easy to be traced by the Receiver. The identification of the sync symbol can be done by comparator or other ADC (Analog to Digital Converter) circuit. Once the sync symbol has been extracted (top Fig. 2), there are two ways to implement the Receiver clock. The fist way is to use PLL as a frequency multiplier and to translate the sync into clock. The second way, which is a part of the disclosed embodiment, is to build an analog frequency multiplier without PLL. As will be shown, the proposed embodiment has an integrated serial to parallel data converter as well. More over, the circuit has the ability to trace fast frequency variations, which therefore makes it much more Jitter resistant.

   The illustration in Fig. 2 are all related to the Receiver side. The incoming stream pass through an input capacitor and the sync signal is created (top Fig. 2). Then, using a frequency divider, phi1 and phi2 are created (Fig. 2). In addition, two saw tooth signals are created (V1, V2). The cre...