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Equalization Method for High-Speed Serial Links

IP.com Disclosure Number: IPCOM000015395D
Original Publication Date: 2002-Jan-11
Included in the Prior Art Database: 2003-Jun-20
Document File: 7 page(s) / 155K

Publishing Venue

IBM

Abstract

The present document describes the equalization of a serial data stream that is transmitted over a channel that has frequency dependent loss characteristics. The transmission channel used in serial link applications is typically a single ended wire, a differential wire pair or an optical channel including laser driver and photo receiver. All of these channels exhibit frequency dependent loss. If a bit stream is transmitted over a channel with frequency dependent loss, then the signal waveform at the receiver shows intersymbol interference (ISI) that can significantly reduce the eye opening. Tight timing margins with increased bit error rates are a result of that. A channel equalizer is a building block that has a frequency dependent gain curve represents the inverse of the loss of the channel, therefore canceling the channel effects. If a signal passes through both the channel and the equalizer, the resulting signal is showing no frequency-dependent loss anymore, and the unwanted ISI is reduced to zero in the ideal case, or to a small value in real world applications. The equalizing block can be located after the channel, in front of the channel or it can even be split with some portion of the equalizing filter be placed on the TX side and some portion on the RX side (Figure 1). Figure 1: Placement of channel equalizer: a) on both sides of the channel, b) after the channel, c) before the channel

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Equalization Method for High-Speed Serial Links

    The present document describes the equalization of a serial
data stream that is transmitted over a channel that has frequency
dependent loss characteristics.

The transmission channel used in serial link applications is
typically a single ended wire, a differential wire pair or an
optical channel including laser driver and photo receiver. All of
these channels exhibit frequency dependent loss. If a bit stream
is transmitted over a channel with frequency dependent loss, then
the signal waveform at the receiver shows intersymbol
interference (ISI) that can significantly reduce the eye opening.
Tight timing margins with increased bit error rates are a result
of that.

A channel equalizer is a building block that has a frequency
dependent gain curve represents the inverse of the loss of the
channel, therefore canceling the channel effects. If a signal
passes through both the channel and the equalizer, the resulting
signal is showing no frequency-dependent loss anymore, and the
unwanted ISI is reduced to zero in the ideal case, or to a small
value in real world applications. The equalizing block can be
located after the channel, in front of the channel or it can even
be split with some portion of the equalizing filter be placed on
the TX side and some portion on the RX side (Figure 1).

Figure 1: Placement of channel equalizer: a) on both sides of
the channel, b) after the channel, c) before the channel

The equalizer is typically realized as a programmable filter, and
this filter is preferably a time domain finite impulse response
(FIR) filter (Figure 2). To adapt the filter response to the
inverse of the channel response, the weights of the FIR filter
have to be programmed to a certain value. The determination of
these weight values is one of the main difficulty when building

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an equalizer, as the adaptation of the weights should happen
automatically either during system initialization or in the
background during normal, undisturbed operation of the link.

Figure 2: High level view of FIR filter

The problem about known equalizers is that the methods described
there are very mathematic and require a digital signal processor
(DSP) for the processing of the data and multi-bit A/D resolution
during signal acquisition. For serial links running at very high
speed, as for example Infiniband links at 2.5GBit/s, DSP's and
multi-bit resolution A/D cannot be realized. Even if the
technology allowed the implementation of circuits that are fast
enough, the power consumption would deny leveraging that
technology, as high-speed serial links have to show very low
power consumption. Examples of efforts to implement equalization
are found in literature or product descriptions. However, all of
the found solutions have either excessive power consumption or
require the coefficients to be non-automatic by user-programming
(, [1] W.J. Dally and J. Poulton, "Transmitter equalization for...