Browse Prior Art Database

PCI Reset Power-Up Glitch Removal

IP.com Disclosure Number: IPCOM000015408D
Original Publication Date: 2002-May-08
Included in the Prior Art Database: 2003-Jun-20
Document File: 4 page(s) / 79K

Publishing Venue

IBM

Abstract

Disclosed is a method for eliminating voltage glitches on PCI Reset lines during system power-up without adding any gate delay to the reset line. This method involves the use of either an NPN Bi-Polar Junction Transistor (BJT), an Open-Collector Driver, or an N-Channel Field Effect Transistor (FET) to force the PCI Reset line to Ground until full voltage is attained on the desired voltage supply. This disclosure only illustrates the NPN Transistor implementation.

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PCI Reset Power-Up Glitch Removal

Disclosed is a method for eliminating voltage glitches on PCI Reset lines during system power-up without adding any gate delay to the reset line. This method involves the use of either an NPN Bi-Polar Junction Transistor (BJT), an Open-Collector Driver, or an N-Channel Field Effect Transistor (FET) to force the PCI Reset line to Ground until full voltage is attained on the desired voltage supply. This disclosure only illustrates the NPN Transistor implementation.

Today's CPU Bridge chips do not guarantee the state of the PCI Reset Line until the device has reached minimum operational voltage. This means that the CPU Bridge could actually drive voltage and current on to the active-low PCI Reset Line, consequently de-asserting PCI Reset, before this bridge chip is operational. Some PCI Adapters use the first de-assertion of this "PCI Reset" signal (without power status qualification) to determine when the adapter should start. This could give the appearance of a malfunctioning adapter card and/or system.

The conventional way of solving this problem involves the use of discreet logic to qualify the PCI Reset line only when system power status is asserted to be good by the power supply. This method, which is illustrated in Figure 1 below, will introduce gate delays on to the PCI Reset Line going to the devices. This additional delay, depending on its magnitude, could cause PCI Timing violations.

- PCI RESET

Standby Voltage

PCI reset plus gate delay

Figure 1: Using a logic gate to qualify the PCI Reset Line

This disclosed method suppresses false de-assertion of the PCI Reset signal during system power-up without

1

 PCI Bridge

> PCIChip

Logic

Gate

Devices

- Sys...