Browse Prior Art Database

Built-in circuit for testing AMLCDs having multiplexed pixels

IP.com Disclosure Number: IPCOM000015410D
Original Publication Date: 2002-Aug-01
Included in the Prior Art Database: 2003-Jun-20
Document File: 2 page(s) / 88K

Publishing Venue

IBM

Abstract

G (k+1) G (k+4)

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Built-in circuit for testing AMLCDs having multiplexed pixels

G (k+1) G (k+4)

     G (k+3) G(k+2) G (k+5) G (k+6)

Display P ixel A rea (A ctive A rea)

GV3 GV2 GV1

YV G

Circuit Area

Display Pixel A rea

Figure 1

G ate-Lines

Data-Lines

D(j+1) D (j+4)

D(j+3)

D(j+2)

R G B

R G B R G

Vcom

pixel-B

G (k+1)

G (k+4)

VcomCs

pixel-A

Cs

TFT

G (k+2)

G (k+3)

Vcom

pixel-B

VcomCs

pixel-A

Cs

TFT

Figure 2

1

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G (k+3n)

G (k+3n+1)

G (k+3n+2)

Figure 3

This article describes a novel switching circuit configuration for image quality inspection of active matrix liquid crystal displays (AMLCDs) cell. The circuit is disposed in peripheral of display pixel area on active matrix substrate of LCD cell. The AMLCD supplies potential from one data-line to two or more pixels controlled by the signals on the same gate-line.

The switching circuit consists of three source buslines connecting to input terminals GV1 to 3, and of TFTs connecting to each gate-line as shown in Figure 1. The TFTs have a common gate-busline connecting to input terminal YVG. The TFT connecting to gate-line G(k+3n+1) is also connecting to terminal GV1, and the like.

These TFTs transmit incoming signals shown in Figure 3 into display pixel area of the multiplexed AMLCD shown in Figure 2. The circuit works by selection potential inputted from the terminal YVG during the image quality inspection of liquid crystal cells. In the meantime, the potential...