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Method for specifying short defect position of gate and common buslines in TFT-LCDs

IP.com Disclosure Number: IPCOM000015425D
Original Publication Date: 2002-Aug-01
Included in the Prior Art Database: 2003-Jun-20
Document File: 2 page(s) / 54K

Publishing Venue

IBM

Abstract

1 x Common Common Common Gate-line Gate-line

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  Method for specifying short defect position of gate and common buslines in TFT-LCDs

1

x

Common Common Common

Gate-line Gate-line

CL CR GL GR

Gate-line ......

Common

Figure 1

This article describes three methods for specifying position of short circuit between gate-line and common-line in AMLCDs with which common-lines and gate-lines are placed by turns in the same layer in parallel. These methods enable to correct the defect at low cost.

Figure 1 shows the short circuit in the AMLCDs. The gate-line resistance (terminals GL to GR) and common-line resistance (terminals CL to CR) are expressed as Rg and Rc in the following descriptions. The three methods are as follows.

(1) CL to GR resistance measurement Based on a measured resistance R1 between the terminals CL and GR as shown in Figure 1, the relative position (x ) of the short circuit is calculated as follow.

R1 = x Rc + (1 - x ) Rg x = (R1 - Rg )/(Rc - Rg)

(2) GL to CR resistance measurement Based on a measured resistance R2 between the terminals GL and CR as shown in Figure 1, the relative position (x ) of the short circuit is calculated as follow.

R2 = x Rg + (1 - x ) Rc x = (R2 - Rc )/(Rg - Rc)

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(3) CL to GL resistance measurement Based on a measured resistance R3 between the terminals CL and GL as shown in Figure 1, the relative position (x ) of the short circuit is calculated as follow.

R3 = x Rc + x Rg x = R3/(Rc + Rg)

It is also possibl...