Browse Prior Art Database

Vertical Structured Clock Buffers for ASICs

IP.com Disclosure Number: IPCOM000015444D
Original Publication Date: 2001-Dec-01
Included in the Prior Art Database: 2003-Jun-20
Document File: 1 page(s) / 39K

Publishing Venue

IBM

Abstract

Clock distribution in an Integrated Circuit (IC) requires careful physical design to reduce latency and clock skew across the chip. Application Specific Integrated Circuits (ASIC) use fixed layout structures called standard cell designs for each circuit element. A standard cell is fixed in both the X and Y. As circuit layouts area needs to increase, additional cells are added in the X direction. For very large circuits, standard cell layouts are implemented as very long (X-direction) and short (Y-direction) rectangles. These large designs are a single cell row in height (Y-direction) and multi cells wide (X-direction).

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 56% of the total text.

Page 1 of 1

Vertical Structured Clock Buffers for ASICs

Clock distribution in an Integrated Circuit (IC) requires careful physical design to reduce latency and clock skew across the chip. Application Specific Integrated Circuits (ASIC) use fixed layout structures called standard cell designs for each circuit element. A standard cell is fixed in both the X and Y. As circuit layouts area needs to increase, additional cells are added in the X direction. For very large circuits, standard cell layouts are implemented as very long (X-direction) and short (Y-direction) rectangles. These large designs are a single cell row in height (Y-direction) and multi cells wide (X-direction).

      When implementing the physical design of a clock tree or some other form of clock distribution, large clock buffers are needed to distribute the system clock across the chip in both the X and Y direction. These Structured Clock Buffers (SCBs) in standard cell layouts are optimized in one of two orthogonal directions. In a Standard Cell Design, an input pin is at the physical center of the SCB. Balanced wires distribute the input to the parallel drivers and an output pin runs the entire physical length of the SCB design. The SCB is used at the end of a branch of a clock tree to drive a group of 20 latches as an example. An optimized chip design would group the latches and balance the wire loads to each latch input thereby minimizing clock latency and skew. Some designs require latches to be grouped in a ve...