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Vertical Structured Clock Buffers for ASICs

IP.com Disclosure Number: IPCOM000015444D
Original Publication Date: 2001-Dec-01
Included in the Prior Art Database: 2003-Jun-20
Document File: 1 page(s) / 39K

Publishing Venue

IBM

Abstract

Clock distribution in an Integrated Circuit (IC) requires careful physical design to reduce latency and clock skew across the chip. Application Specific Integrated Circuits (ASIC) use fixed layout structures called standard cell designs for each circuit element. A standard cell is fixed in both the X and Y. As circuit layouts area needs to increase, additional cells are added in the X direction. For very large circuits, standard cell layouts are implemented as very long (X-direction) and short (Y-direction) rectangles. These large designs are a single cell row in height (Y-direction) and multi cells wide (X-direction). When implementing the physical design of a clock tree or some other form of clock distribution, large clock buffers are needed to distribute the system clock across the chip in both the X and Y direction. These Structured Clock Buffers (SCBs) in standard cell layouts are optimized in one of two orthogonal directions. In a Standard Cell Design, an input pin is at the physical center of the SCB. Balanced wires distribute the input to the parallel drivers and an output pin runs the entire physical length of the SCB design. The SCB is used at the end of a branch of a clock tree to drive a group of 20 latches as an example. An optimized chip design would group the latches and balance the wire loads to each latch input thereby minimizing clock latency and skew. Some designs require latches to be grouped in a vertical direction instead of a horizontal directions. This is common in boundary scan latches along the east or west side of an IC driving perimeter I/Os or when latches are bit stacked in a vertical layout. Wiring from the SCB to vertical latched can be a problem to balance. A second level of metal is required to make the right angle turns and more wire is needed to wire and balance the clock signal to the latches. SCBs can be mirrored or flipped about the X and Y directions, but any combination of possible placements still leaves a horizontal layout of the SCB. To solve this problem a family of Vertical SCBs was developed that have the same electrical characteristics of the SCBs, but are physically layed out in the Y direction. Because such a layout would violate the standard cell definitions, the vertical SCBs were implemented as a macro or core to fit the ASIC methodology. Figure 1 shows the Vertical SCB driving a group of latches in a much more efficient manner. A group clock buffers that contains both SCBs and Vertical SCBs allows for better clock optimization, reduced latency, reduced clock skew and less global wiring to distribute the clock signals. 1

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Vertical Structured Clock Buffers for ASICs

Clock distribution in an Integrated Circuit (IC) requires careful physical design to reduce latency and clock skew across the chip. Application Specific Integrated Circuits (ASIC) use fixed layout structures called standard cell designs for each circuit element. A standard cell is fixed in both the X and Y. As circuit layouts area needs to increase, additional cells are added in the X direction. For very large circuits, standard cell layouts are implemented as very long (X-direction) and short (Y-direction) rectangles. These large designs are a single cell row in height (Y-direction) and multi cells wide (X-direction).

      When implementing the physical design of a clock tree or some other form of clock distribution, large clock buffers are needed to distribute the system clock across the chip in both the X and Y direction. These Structured Clock Buffers (SCBs) in standard cell layouts are optimized in one of two orthogonal directions. In a Standard Cell Design, an input pin is at the physical center of the SCB. Balanced wires distribute the input to the parallel drivers and an output pin runs the entire physical length of the SCB design. The SCB is used at the end of a branch of a clock tree to drive a group of 20 latches as an example. An optimized chip design would group the latches and balance the wire loads to each latch input thereby minimizing clock latency and skew. Some designs require latches to be grouped in a ve...