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Soft Error Resistant Latch

IP.com Disclosure Number: IPCOM000015445D
Original Publication Date: 2001-Dec-01
Included in the Prior Art Database: 2003-Jun-20
Document File: 1 page(s) / 36K

Publishing Venue

IBM

Abstract

The soft error resistant latch is a modified version of an latch which uses the master-slave configuration, so there are really two latches that make up one latch. Also, the latches are basically cross-coupled inverters so both data input and the inverse of the data input are stored at the critical nodes of both latches. Transistors are placed in series with the branches to the VDD and ground rails to prevent the wrong path from conducting if there is a charge injected at a critical node that would normally cause a soft error. Node names and what they mean: L1_T The node of the first latch that has the same value as the data. L1_C The node of the first latch that has the inverse value of the data. L2_T The node of the second latch that has the same value as the data.

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Soft Error Resistant Latch

   The soft error resistant latch is a modified version of an latch which uses the master-slave configuration, so there are really two latches that make up one latch. Also, the latches are basically cross-coupled inverters so both data input and the inverse of the data input are stored at the critical nodes of both latches. Transistors are placed in series with the branches to the VDD and ground rails to prevent the wrong path from conducting if there is a charge injected at a critical node that would normally cause a soft error.

Node names and what they mean: L1_T - The node of the first latch that has the same value as the data.

L1_C - The node of the first latch that has the inverse value of the data.

L2_T - The node of the second latch that has the same value as the data.

L2_C - The node of the second latch that has the inverse value of the data.

For an example of what is done in the design, take the inverter in the first latch whose gate is connected to L1_T and whose output is L1_C. A series PFET is placed between VDD and the PFET normally in the inverter, and a series NFET separates GND and the NFET already in the inverter. The gates of the two new transistors are connected to L2_T.

Now say the data input is a logical 1. This means L1_T and L2_T would open the path to ground and hold L1_C to a logical 0. Also, the path to VDD is turned off because the gate of the new PFET is now at VDD. A negative charge injected to L1_T would normally turn on the path to VDD, but because of the new PFET, that path is blocked. Once the charge disappears, L1_T will return to a logical 1 since L1_C is still at a logical 0.

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