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# Method to generate synchronization signal for multiple clock domains

IP.com Disclosure Number: IPCOM000015467D
Original Publication Date: 2002-Mar-30
Included in the Prior Art Database: 2003-Jun-20
Document File: 1 page(s) / 39K

IBM

## Abstract

Logic that uses two synchronous clock domains often needs a synchronization signal to indicate the relationship the current cycle is relative to the other clock domain. A simple method to generate this synchronization is described. If two synchronous clocks had a 3:1 ratio, for example, the logic in the faster clock may need to know if it is the first, second, or third cycle within the slower clock's cycle. This method uses two flip-flops, one clocked by each clock domain, plus an inverter and an exclusive-OR gate, as shown in the figure. The timing diagram in the figure shows a 2:1 ratio, but any ratio may be used with this to get a single fast cycle pulse during the first fast cycle within the slow cycle. To identify other cycles for higher ratios, a counter clocked by the fast clock and set to 0 with this sync signal would indicate the fast cycle number within the slow cycle. (HARDCOPY FIGURE SENT TO GIA VO 1/30/02) 1

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Method to generate synchronization signal for multiple clock domains

Logic that uses two synchronous clock domains often needs a synchronization signal to indicate the relationship the current cycle is relative to the other clock domain. A simple method to generate this synchronization is described.

If two synchronous clocks had a 3:1 ratio, for example, the logic in the faster clock may need to know if it is the first, second, or third cycle within the slower clock's cycle. This method uses two flip-flops, one clocked by each clock domain, plus an inverter and an exclusive-OR gate, as shown in the figure. The timing diagram in the figure shows a 2:1 ratio, but any ratio may be used with this to get a single fast cycle pulse during the first fast cycle within the slow cycle. To identify other cycles for higher ratios, a counter clocked by the fast clock and set to 0 with this sync signal would indicate the fast cycle number within the slow cycle.

(HARDCOPY FIGURE SENT TO GIA VO 1/30/02)

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