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Low capacitance ESD diodes formed in ZeroVT well

IP.com Disclosure Number: IPCOM000015556D
Original Publication Date: 2002-Oct-17
Included in the Prior Art Database: 2003-Jun-20
Document File: 6 page(s) / 98K

Publishing Venue

IBM

Abstract

Disclosed is a method for forming a low capacitance Electro-Static Discharge (ESD) protection diode in a CMOS logic technology based on a p- substrate without an epitaxially grown p+ top layer. A special silicon well doping procedure is used to create a low-doped well in the region of the diode. The special well type used, referred to as the ZeroVT well, is actually the blocking of both the p-type well (Pwell) and n-type well (Nwell) implants so there is no additional process cost incurred by forming the lower capacitance diode . N+ diffusion in substrate (N+/SX) and Nwell in substrate (NW/SX) p-n junction diodes are commonly used to provide an Human Body Model (HBM) ESD protection path between input or I/O pads and the Vss or GND supply rails. One of the main disadvantages of adding such a diode to the input or I/O pad, particularly in RF circuits, is the parasitic capacitance associated with the diodes. This invention provides a method to reduce the amount of capacitance associated with the diodes while still maintaining adequate performance for ESD protection. Fig. 1 shows a typical HBM ESD protection strategy using the non-self protecting diode implementation. The HBM ESD capacitive loading is determined by the loading of diode 1 to Vdd AND the loading of diode 2 to Vss. Typically diode 1 to Vdd is a P+/NW diode with perimeter in the 300um to 600um range to achieve 2KV HBM protection in positive mode, leading to capacitive loading values of 150fF to 350fF on average. Diode 2 to Vss is either a N+/SX or NW/SX with perimeter typically in the 100um to 200um range to achieve 2KV in negative mode HBM, leading to capacitive loading values of 100fF to 150fF on average. The ZeroVt well is used to create lower doping at the p-n junction in the N+/SX or NW/SX diode to reduce it's parasitic capacitance. The placement of the ZeroVt well depends on whether the diode being used is an N+/SX or NW/SX diode. Figs. 2 and 3 detail the case of the N+/SX diode. In the standard N+/SX diode layout, the N+ diffusion 3 is created inside the Pwell 4 and is surrounded by a local P+ diffusion contact 5 to the Pwell. The p-n junction forms between the N+ diffusion 3 and the Pwell

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Low capacitance ESD diodes formed in ZeroVT well

Disclosed is a method for forming a low capacitance Electro-Static Discharge (ESD) protection diode in a CMOS logic technology based on a p- substrate without an epitaxially grown p+ top layer. A special silicon well doping procedure is used to create a low-doped well in the region of the diode. The special well type used, referred to as the ZeroVT well, is actually the blocking of both the p-type well (Pwell) and n-type well (Nwell) implants so there is no additional process cost incurred by forming the lower capacitance diode .

N+ diffusion in substrate (N+/SX) and Nwell in substrate (NW/SX) p-n junction diodes are commonly used to provide an Human Body Model (HBM) ESD protection path between input or I/O pads and the Vss or GND supply rails. One of the main disadvantages of adding such a diode to the input or I/O pad, particularly in RF circuits, is the parasitic capacitance associated with the diodes. This invention provides a method to reduce the amount of capacitance associated with the diodes while still maintaining adequate performance for ESD protection.

Fig. 1 shows a typical HBM ESD protection strategy using the non-self protecting diode implementation. The HBM ESD capacitive loading is determined by the loading of diode 1 to Vdd AND the loading of diode 2 to Vss. Typically diode 1 to Vdd is a P+/NW diode with perimeter in the 300um to 600um range to achieve 2KV HBM protection in positive mode, leading to capacitive loading values of 150fF to 350fF on average. Diode 2 to Vss is either a N+/SX or NW/SX with perimeter typically in the 100um to 200um range to achieve 2KV in negative mode HBM, leading to capacitive loading values of 100fF to 150fF on average. The ZeroVt well is used to create lower doping at the p-n junction in the N+/SX or NW/SX diode to reduce it's parasitic capacitance. The placement of the ZeroVt well depends on whether the diode being used is an N+/SX or NW/SX diode.

Figs. 2 and 3 detail the case of the N+/SX diode. In the standard N+/SX diode layout, the N+ diffusion 3 is created inside the Pwell 4 and is surrounded by a local P+ diffusion contact 5 to the Pwell. The p-n junction forms between the N+ diffusion 3 and the Pwell
4. Disclosed is an alteration of this design by adding a design layer to create the ZeroVT well 6 below the N+diffusion 3. This ZEROVT shape is added arou...