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Regulated Delay Line with Look-Up Table

IP.com Disclosure Number: IPCOM000015689D
Original Publication Date: 2002-Apr-01
Included in the Prior Art Database: 2003-Jun-21
Document File: 2 page(s) / 62K

Publishing Venue

IBM

Abstract

Disclosed is an architecture of Regulated Delay Line to be composed on digital Integrated Circuit. This architecture provides application logic designers, especially designers using Gate Array, with an easy way to compose a Delay Line stabilized against variation of operating temperature, operating voltage, and manufacturing process. Delay Locked Loop (DLL) circuit is not used here, but an open loop control with a programmable Look Up Table achieves stability of propagation delay in Delay Line, which allows more flexibility than one using DLL. Pin pulse width Tpw Delay Measurement Circuit

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Regulated Delay Line with Look-Up Table

Disclosed is an architecture of Regulated Delay Line to be composed on digital Integrated Circuit.

This architecture provides application logic designers, especially designers using Gate Array, with an easy way to compose a Delay Line stabilized against variation of operating temperature, operating voltage, and manufacturing process. Delay Locked Loop (DLL) circuit is not used here, but an open loop control with a programmable Look Up Table achieves stability of propagation delay in Delay Line, which allows more flexibility than one using DLL.

Pin ( pulse width = Tpw )

   Delay Measurement Circuit

Npw

Ndelay

SignalProgrammable Delay Line Delayed Signal

Fig 1. Architecture of Regulated Delay Line

 Look Up Table (Programmable)

t

The Fig 1 shows the architecture, in which Regulated Delay Line consists of three functional blocks, i.e. (1) Programmable Delay Line, (2) Delay Measurement Circuit, and (3) Look Up Table.

The Ndelay, in the Fig 1, is a number to be set to the Programmable Delay Line and determines the propagation delay ( Tdelay ) in the P.D.L.. Because the Tdelay varies under variation of operating temperature, operating voltage, and manufacturing process, the Ndelay needs to be adjusted to maintain Tdelay on a target value. A number of Ndelay, with which Tdelay is at a target value under a condition, can be determined by a simulation with actual delay information, which is one of results of Physical Design( PD ), i.e. component placement and signal routing.

The Delay Measurement Circuit measures width of a pulse ( Pin ) assured to have a constant and known width ( Tpw ). The Npw is a number put out from Delay Measurement Circuit, i.e. the result of measuring Tpw. The Npw varies under variation of operating temperature, operating voltage, and manufacturing process so that it is a reflection of current condition of chip. A number of Npw under a conditions can also be determined by a simulation with actual delay information. The Fig 2 shows an example of the Delay Measurement Circuit.

Let's assume Ndelay needs to be Ndelay(n) to set the Programmable Delay Line having a target propagation delay under a condition, suffixed 'n', of operating temperature, operating voltage, and manufacturing...