Browse Prior Art Database

Write ECC dump with buffered correction

IP.com Disclosure Number: IPCOM000015694D
Original Publication Date: 2002-Feb-20
Included in the Prior Art Database: 2003-Jun-20
Document File: 4 page(s) / 45K

Publishing Venue

IBM

Abstract

This article describes a written ECC(Error Correcting Code) dump method to clarify the written ECC before is wrong or not when a system has a buffer SRAM for on-the-fly correction by using vacant area on the SRAM at media writing without gate increasing.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 41% of the total text.

Page 1 of 4

Write ECC dump with buffered correction

This article describes a written ECC(Error Correcting Code) dump method to clarify the written ECC before is wrong or not when a system has a buffer SRAM for on-the-fly correction by using vacant area on the SRAM at media writing without gate increasing.

Block diagram of a system has a buffer SRAM for on-the-fly correction is shown as below.

+------------------------------+

| DRIVE CONTROL |------------------------------------------+
+------------------------------+ |

    | | |
|ECC code +-----------+ |
| | | |
V V |USER DATA |
+-------------------+ | |
| ECC Processor | | |
+-------------------+ | |

          | | |
V | |
+---------+--------+ | |
|Location0|Pattern0| | |
+---------+--------+ | |WRITE

     ........... | |REQUEST
+---------+--------+ | |
|LocationX|PatternX| +-----------------------------------+ |
+---------+--------+ | |

          | | |
V | V
+------------------+ +--------------+ +---------------+ | +-------------+
| Locaton/Pattern | | Read Address | | Write Address | | | ARBITRATION |
| Selector |<----| Register | | Register |<-----+--| CONTROL |
+------------------+ +--------------+ +---------------+ | | +-------------+

|| | | | | A
|| V V | | |
| | ------+----- <-----------------+ |READ
| | |Address | | |REQUEST
|| V | | |

| | +-----------------+ R/W | | |
| | | |<-------------+ |
| | | DRIVE BUFFER |DIN | |
| | | 2KB SRAM |<-----------+ |
|| | | |
|| | | |
|| | | |
| | +-----------------+ |
| |On-the-fly correction |DOUT |
| +----------------------------->+ |
| | |
| V |
|TRANSFER REQUEST +-----------------+ |
+--------------------------->| MEMORY CONTROL |---------------------+

+-----------------+

A system has a buffer SRAM for on-the-fly correction can reduce read-modify-write cycle for on-th-fly correction from main memory(DRAM etc) band width. This means the system can support higher data transfer date than the conventional one by using same main memory.

1

Page 2 of 4

The block diagram of this invention is shown as below.

+------------------------------+

| DRIVE CONTROL |--------------------------------------------+
+------------------------------+ |

    | | | USER DATA |
|ECC code +------|----+-----------------------------------+ |
|(read) | | | |
V V +------+ | |
+-------------------+ |LBA | |
| ECC Processor | | | |
| |ECC code | +---------------+ | |
| +-----------+ |(write) +-->| DUMP DATA | DUMP DATA | |
| |Parity Gen.|--------------|-->| Selector |------------>+ |
| +-----------+ | | +---------------+ | |
+-------------------+ | A | |

          | V |DUMP_START | |
V +----------------+ R/W REQUEST | |
+---------+--------+ | LBA comparator |--------------------------+ |
|Location0|Pattern0| +----------------+ | | |WRITE
+---------+--------+ A A | | |REQUEST

     ........... | | TARGET_LBA | | |
+---------+--------+ | +----------------------------+ | |
|LocationX|PatternX| TARGET_LBA_ENABLE | | | |
+---------+--------+ | | | |

          | +-----------------------------------+ | | | |
V | Dump Address controller | | | V V
+------------------+ |+--------------+ +--------------...