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Interrupt Scheduler for processor with cache

IP.com Disclosure Number: IPCOM000015696D
Original Publication Date: 2002-Apr-01
Included in the Prior Art Database: 2003-Jun-20
Document File: 2 page(s) / 63K

Publishing Venue

IBM

Abstract

Disclosed is the method to reduce the overhead of the interrupt process with just interrupt controller changing.

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Interrupt Scheduler for processor with cache

   Disclosed is the method to reduce the overhead of the interrupt process with just interrupt controller changing.

In traditional method, all of interrupt handling process are performed at the time when the interrupt occurred. But most of the interrupt handling process have not to respond to the interrupt immediately. In this disclosure method, each original interrupt source is latched at the interrupt controller, then the latched interrupt is provided to the delay logic. Each delay logic has each programmable delay timing. The ORed signal of each delay logic output is provided to the processor. The processor performs to the interrupt handling process of all of the interrupt latched in the interrupt controller. This method can eliminate the number of suspend and resume process by the interrupt.

The following figure 1 and 2 indicates the timing chart and the block diagram.

Figure 1

Interrupt Schedule

Interrupt A Interrupt B Interrupt C

Current Logic Interrupt to CPU

Interrupt A Delay Interrupt B Delay Interrupt C Delay

New Logic Interrupt to CPU

A B C AC B AC

A,B,C A,C A,B C

Figure 2

1

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New Interrupt Logic

Delay B

Delay C

Interrupt to CPU

Interrupt A Status to CPU

Interrupt B Status to CPU

Interrupt C Status to CPU

 OR Logic

Delay A

FlipFlop

FlipFlop

FlipFlop

IN Q

Interrupt A

Clear Interrupt A from CPU

Interrupt B

Clear Interrutp B from CPU

Interrupt C

C...