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SPI-4 control word insertion in a regular data flow

IP.com Disclosure Number: IPCOM000015772D
Original Publication Date: 2002-Oct-04
Included in the Prior Art Database: 2003-Jun-21
Document File: 2 page(s) / 81K

Publishing Venue

IBM

Abstract

In most of the communication protocols there is a mix of raw data and control words in the same bus. The control words are aimed to add some meaning to the transported data. When high data rate are requested, it is common practice to have the raw data prepared at a lower frequency and have a 2x data path. This is possible due to the fact that most of the time the data flow is regular. The drawback of having to insert control words is that this regular flow is broken. Here is a description of how to insert control words in the data flow without impacting the regularity of the data flow. To that end, the data path and the control path are kept separate up to the time the data is ready to be sent and the control word must be inserted. Now turning to Figure 1, the join circuit receives 2 data word (via the data path) by clock cycle and the control word (via the control path). Every clock cycle, a new set of data is provided while a control word is provided only from time to time. (see Figure 1) d0 d1 ctl1 d2 d3 d6

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SPI-4 control word insertion in a regular data flow

In most of the communication protocols there is a mix of raw data and control words in the same bus. The control words are aimed to add some meaning to the transported data. When high data rate are requested, it is common practice to have the raw data prepared at a lower frequency and have a 2x data path. This is possible due to the fact that most of the time the data flow is regular. The drawback of having to insert control words is that this regular flow is broken. Here is a description of how to insert control words in the data flow without impacting the regularity of the data flow.

To that end, the data path and the control path are kept separate up to the time the data is ready to be sent and the control word must be inserted. Now turning to Figure 1, the join circuit receives 2 data word (via the data path) by clock cycle and the control word (via the control path). Every clock cycle, a new set of data is provided while a control word is provided only from time to time. (see Figure 1)

d0 d1 ctl1 d2 d3

d6
d7

ctl2

Figure 1

Every time a control word is input, a hold command is sent back to the data path and the control path. This hold command is used to spare one clock cycle where the control word will be inserted. This is done thru the FSM protocol shown in Figure 2. The FSM circuit shown in Figure 3 is a typical implementation, it just consists of a 2 stage pipeline with a multiplexor . The combination of th...