Browse Prior Art Database

Sorting by index register for buffered correction

IP.com Disclosure Number: IPCOM000015795D
Original Publication Date: 2002-Mar-14
Included in the Prior Art Database: 2003-Jun-21
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Abstract

This article describes an on-the-fly correction method by using index register sorting for the system employs the buffered correction and reduce complexity brought by unmatch of bus width of SRAM and interleave number.

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Sorting by index register for buffered correction

This article describes an on-the-fly correction method by using index register sorting for the system employs the buffered correction and reduce complexity brought by unmatch of bus width of SRAM and interleave number.

Block diagram of a system has this invention is shown as below.

+--------------------+

                         | Syndrome Generator |
Codeword(DATA + ECC) ---->| and CRC Generator |

| +--------------------+
| |

| | Syndrome, CRC Syndrome
| V +------------------+
| +------------------------+ Error Location and Pattern | Location/Pattern |
| | Decoder |------+-------------------->| registers |
| | | | +------------------+
| | | |Error Location | |

| | Euclid,Chien search | V | |
| | and CRC Verify |-+ +-------+ V |
| +------------------------+ | |Offset | +----------+ |
| Correction Area +->|counter|Offset/column|Index | |
| |/column|------------>|register | |
| +-------+ |creation | |
| DATA +------------------+ |+--------+| |
+----------------->| Buffer control | +---+ +--------+ Index ||Index || |

| +--------------+ |--->|XOR|<----| OTF |<-------||register|| |
| | Buffer(SRAM) | | +---+ | control| |+--------+| |
| +--------------+ | | +--------+ +----------+ |
+------------------+ | A |

| | Error Pattern|
| +----------------------------+
V Corrected data

Additional block for this invention is only Offset counter/column and Index register creation. Contents of index register is shown as below.

OFS_COL1 OFS_COL2 OFS_COL3

             | | |
ERN_COL0 V ERN_COL1 V ERN_COL2 V ERN_COL3
<------------><------------><-----------><----------->

       A +------------+-------------+------------+------------+
? bits | | Column 0 | Column 1 | Column 2 | Column 3 |

V +------------+-------------+------------+------------+

| \ Contents of index register indicates register number of error
| \ location and pattern that belong column x.

          | \ ? is decided by correctable capability.
example V V

+---+---+---+---+

|0|3|4|7| Left example shows error location and pattern register
+---+---+---+---+ 0,3,4 and 7's erros belog column 0.

In above example, column is set to 4. (This means SRAM bus width is·quadruple of interleave number case) OFS_COL1,2 and 3 is contents of offset counter/column and indicates start address of each column in index register. If decoder finds the error location and this is correction target during chien serach, Offset counter/column increases

appropriate OFS_COLx value. Index register creation constructs index registers by using OFS1,2 and 3 at index register creation phase. On-the fly control block diagram is shown as below.

1

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On-the-fly control Block diagram

                                  Index register for column1(#1)
Error location and +---+---+---+---+---+---+---+
pat...