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Automatic Reset of a Processing Unit after a Parity Check without loosing Error Data Disclosure Number: IPCOM000015827D
Original Publication Date: 2002-Mar-18
Included in the Prior Art Database: 2003-Jun-21
Document File: 3 page(s) / 47K

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  Automatic Reset of a Processing Unit after a Parity Check without loosing Error Data


    Registers of a processing unit are protected with additional hardware against soft or hard errors. Even or odd parity generation and checking is a very common approach to detect this kind of errors.

    The occurrence of parity checks lead to an error condition which is indicated to software. Software is then responsible to handle and reset the error condition in hardware.

    The current hardware approach automatically performs a reset of the processing hardware unit after the occurrence of a parity check and provides the requesting unit the error data for fault analysis.

    A retry of the requested operation could be performed without any reset commands to the failing unit from software.

Hardware Overview:

    Figure 1 gives an overview of the logic implementation. A Control Finite State Machine (Ctrl FSM) is responsible for the handling of the external control signals to and from a requesting unit. Input control signal is a request signal which is responsible for the start of the processing unit. Output control signals are acknowledge and error. The acknowledge signal informs the requesting unit about the successful execution of a request by the processing unit. The error signal indicates an error during the execution phase of the processing unit. The acknowledge or the error signal to the external requesting unit signals the end of execution of the processing unit. The processing unit reaches an idle state, which indicates that the processing unit is able to accept the next request for the execution of an operation. Figure 2 and 3 are showing timing diagrams for a normal sequence and an error sequence.

    The processing unit switches between different operation modes in dependence of the external opcode. Internally a control bus between the Ctrl FSM and the processing logic is responsible for the execution of different opcodes as requested by the external unit.

A data bus (data_in) serves as input from the processing unit for data routing. The data_in bus is directly connected to the processing logic. Data_in must be stable when the request signal is asserted.

    A data bus (data_out) serves as output to the processing unit for data routing. Data_out must be stable when the acknowledge or the error signal is asserted. The...