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Driver circuit suitable for variable capacitance loads

IP.com Disclosure Number: IPCOM000015885D
Original Publication Date: 2002-Jun-01
Included in the Prior Art Database: 2003-Jun-21
Document File: 2 page(s) / 73K

Publishing Venue

IBM

Abstract

Disclosed is a driver circuit suitable for variable capacitance loads. In general a higher slew rate makes a bigger margin of setup/hold time, but causes serious overshooting and bounce noise for some data patterns, so it finally reduces setup/hold time. The transfer rates are 33, 66, 100 and 133MB/s in Ultra DMA mode. The slew rate of an ATA bus driver is selected to match the transfer mode, using a kind of flat cable.

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Driver circuit suitable for variable capacitance loads

Disclosed is a driver circuit suitable for variable capacitance loads.

In general a higher slew rate makes a bigger margin of setup/hold time, but causes serious overshooting and bounce noise for some data patterns, so it finally reduces setup/hold time.

The transfer rates are 33, 66, 100 and 133MB/s in Ultra DMA mode.

The slew rate of an ATA bus driver is selected to match the transfer mode, using a kind of flat cable.

An ATA flat cable is connected with a master device and a slave device.

In current design the slew rate depends on whether there is or not a slave device.

If the slew rate is selected without a slave device, the slew rate with the slave device is reduced, so the margin of the setup/hold time is reduced.

This circuit is designed to match variable capacitance loads.

Figure 1 shows the block diagram of this design.

Figure 1. Block Diagram of Pull-up Pre-Driver

When INPUT = High, and OUTPUT = Low the added NFET1 (Gray colored) is ON, boosting the rising slew rate.

For heavy capacitance load the rising slew rate is small, so the interval time (INPUT high => OUTPUT high) is long.

This NFET1 is ON for a long time, so the rising slew rate is restored.

For light capacitance load this circuit makes no differences.

Figure 1 shows only a Pull-up Pre-driver, but same method is used for the Pull-down Pre-Driver (A PFET1 is added).

Figure 2 shows the simulation results of the functioning of this method.

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