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On-Chip Driver output slew rate measurement method

IP.com Disclosure Number: IPCOM000015886D
Original Publication Date: 2002-Sep-22
Included in the Prior Art Database: 2003-Jun-21
Document File: 3 page(s) / 75K

Publishing Venue

IBM

Abstract

On-Chip Driver output slew rate measurement method is described. Recently the Driver that has some slew rate control or the slew rate is important has been developed. To measure the slew rate of such Driver, some special instruments are required. By using this new method, it is possible to measure slew rate without any additional instruments and it also can be measured "On-Chip". Figure-1 shows the new proposed circuit. Figure-2 shows the timing chart of each node. As shown in the figure, Driver output is fed back into the circuit on the same chip. And then it becomes possible to measure Driver output slew rate on the same chip.

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On-Chip Driver output slew rate measurement method

On-Chip Driver output slew rate measurement method is described.

Recently the Driver that has some slew rate control or the slew rate is important has been developed. To measure the slew rate of such Driver, some special instruments are required. By using this new method, it is possible to measure slew rate without any additional instruments and it also can be measured

"On-Chip".

Figure-1 shows the new proposed circuit. Figure-2 shows the timing chart of each node. As shown in the figure, Driver output is fed back into the circuit on the same chip. And then it becomes possible to measure Driver output slew rate on the same chip.

A basic procedure is described below.
1) Set "0" or "1" on Driver-in at a slew rate measurement mode.

2) Compare the output voltage at PAD to Vcl and Vch by two comparators. Where Vcl and Vch are the lower voltage and the upper voltage of the slew rate measurement. The comparator outputs "1" when inputs are (+) >(-), and outputs "0" when inputs are (+)<(-).

3) Input the comparators outputs, CL_OUT and CH_OUT, into XOR. Then XOR outputs "1" when PAD voltage is at Vcl<PAD<Vch, and outputs "0" at the other voltage.

  PAD voltage CL_OUT CH_OUT SR_IN PAD<Vcl 0 0 0 Vcl<PAD<Vch 1 0 1

VchPAD 1 1 0

4) Reset Shift Registers to"0" and inputs XOR output, SR_IN into Shift Registers. When PAD is at Vcl<PAD<Vch, "1" is stored and shifted in Shift Registers. Then the bit stream in Shift Registers becomes li...