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An Enable Signal Circuit for Multiple Small Banks Disclosure Number: IPCOM000015887D
Original Publication Date: 2002-Jun-01
Included in the Prior Art Database: 2003-Jun-21
Document File: 4 page(s) / 68K

Publishing Venue



Title of Disclosure : An Enable Signal Circuit for Multiple Small Banks Inventor : Toshio Sunaga, Shinpei Watanabe, Kohji Hosokawa

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An Enable Signal Circuit for Multiple Small Banks

Title of Disclosure : An Enable Signal Circuit for Multiple Small Banks
Inventor : Toshio Sunaga, Shinpei Watanabe, & Kohji Hosokawa

    For DRAM chips that consist of many small-sized banks, this disclosure
provides an area-efficient circuit method to activate those small banks.

   The previous invention proposed a virtual bank method as an effective way
to achieve high data rates for random row accesses (1). In this architecture,
the chip consists of many small array blocks, where a self-timed circuit in
each block controls the whole timing chain including row address latch, sense
amplifier activation, write-back, and precharge, thus those blocks work as if
there were many banks. It realizes multiple bank access operations without
complex bank control schemes found in conventional DRAMs. When conventional
methods to activate those many banks are exploited, many bank enable signal
lines become necessary to wire all over the chip, and this causes a
significant impact on chip size. Fig. 1 shows three examples of those
conventional schemes. In the DRAM chip, there are four large blocks, and each
block is sectioned further into 256 banks (32 in horizontally and eight in
vertically). Thus, the chip has 1,024 small banks. In actual implementation, a
segmented row decoder with M1 main word lines and 4-8 polycide word lines per
each main word line is assumed. To operate those banks independently, there
is a control circuit at the corner surrounded by a sense amplifier block and
the segmented row decoder in each bank. For each bank, it is necessary to
provide a bank enable signal, and it requires some circuits and wiring areas.


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1. Simple 32 Bank Enable Lines

Bank Enable Signal

Bank Enable Signal

M1 Main Row Decoder

16 Banks

One Bank







Word Lines

Sense Am plifiers

i nes

Bi t L

2. Locally Generated Bank Enable Signal

with 10 Pre-decoded Lines


32 B

32 B


Enable Circuit

Bank Control Circuit Block

Bank Enable Signal

   A scheme shown in Fig.1-1 is the simplest example, where there are 32 bank
enable signal lines for 32 banks placed vertically in the four large blocks of
the chip. Since there are 32 columns for those 32 banks, the chip needs 1,024
wires for the enable signals, and it causes to increase the die size. In stead
of the simple 32 lines per 32-bank column, the second example shown in Fig.1-2
uses 10 predecoder output lines from 5-bit bank address for 32 banks. The
predecoder is located at the bottom of the four large blocks. Although the
signal lines can be reduced from 32 to 10, each bank needs an area for the
10-input AND circuits. Fig.1-3 shows the last example to wire 5 bank address
lines in the 32-bank column and to decode them in each bank locally. If it is
assumed that the bank address increments from bottom to top and LSB is
assigned to the right edge line of the 5 bank address wires, the shown bank
placed at 8th from the bottom has a decoder that consists of a 5-input AN...