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Method to Provide Exclusive Access to a Shared I2C Bus Resource (I2C MUTEX)

IP.com Disclosure Number: IPCOM000015947D
Original Publication Date: 2002-May-08
Included in the Prior Art Database: 2003-Jun-21
Document File: 2 page(s) / 56K

Publishing Venue

IBM

Abstract

In today's I2C bus structure there is no architected way to obtain exclusive access to any I2C bus resource. Any I2C master may read and write to any device without concern for what other agents may be doing. This may lead to a situation where a device that needs multiple separate transactions to perform an operation may be corrupted by multiple I2C masters accessing the device.

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Method to Provide Exclusive Access to a Shared I2C Bus Resource (I2C MUTEX)

In today's I2C bus structure there is no architected way to obtain exclusive access to any I2C bus resource. Any I2C master may read and write to any device without concern for what other agents may be doing. This may lead to a situation where a device that needs multiple separate transactions to perform an operation may be corrupted by multiple I2C masters accessing the device.

This invention will allow multiple I2C masters that follow the "I2C MUTEX semaphore protocol" to arbitrate and gain exclusive access of a shared I2C resource. The invention is composed of an I2C based memory device, control logic to prevent multiple I2C masters from setting their semaphore bit and a protocol to ensure serialized access to a different I2C resource.

The invention is built such that an I2C master can read and write data to the device using the standard Philips I2C protocol. To the I2C masters the invention looks like a standard I2C based memory device. The can support as few as two masters and is only limited in size by the number of I2C master that require access to the shared resource. Each I2C master is assigned a bit in the invention with the highest priority master owning the MSB. No two I2C masters can share a bit. Each I2C master is assigned a different bit since by the I2C arbitration rules, two different I2C masters can successfully write the same data to a device during the exact same I2C bus transaction. If a single bit were to be used, two I2C masters could presume that they each have e...