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Voltage Plane Sequence Detect Circuit for TCPA Root-of-Trust-Measurement (RTM)

IP.com Disclosure Number: IPCOM000016003D
Original Publication Date: 2002-May-16
Included in the Prior Art Database: 2003-Jun-21
Document File: 2 page(s) / 69K

Publishing Venue

IBM

Abstract

In Client PCs based on the Trusted Computing Platform Alliance (TCPA) specification, trusted such as private keys, digital certificates, random number generation and protected storage is synchronized at power-up through the use of an immutable portion of BIOS initialization code that is called the Root-of-Trust Measurement or RTM. In PC Clients that implement power

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  Voltage Plane Sequence Detect Circuit for TCPA Root-of-Trust-Measurement (RTM)

In Client PCs based on the Trusted Computing Platform Alliance (TCPA) specification, trusted

such as private keys, digital certificates, random number generation and protected storage is

synchronized at power-up through the use of an immutable portion of BIOS initialization code

that is called the Root-of-Trust Measurement or RTM. In PC Clients that implement power

management techniques, the motherboard subsystems are usually isolated on unique voltage

plane islands that are powered up and down through a defined sequence of motherboard

voltage plane connections to the main power supply. In most cases a hardware controller

manages the activation of the voltage planes and this activity occurs prior to the RTM

initialization BIOS acquires control of the motherboard. This pre-RTM voltage bring-up

could be used to corrupt the establishment of the RTM synchronization of the PC Client.

The problem solved by the circuit is to provide the RTM a measurable hardware bit that if asserted indicates that the motherboard voltage plane islands where powered up in the correct sequence defined by the motherboard manufacturer and prevent hacker attacks that would circumvent this sequence and possibly insert bogus code prior to initialization, for example.

The circuit consists of a group of Set/Reset Latches that reside in the Power Management enabled Power Supply subsystem. The latches are powered by the Power Supply subsystem and are reset by the reset cycle within this subsystem. The output of the latches, one for each island voltage plane to be monitored on the motherboard, are connected to an AND gate whose output is called "Sequence Correct" bit. Each Latch set input is connected to NAND gate that resides in the island voltage planes to be monitored for the correct motherboard manufacturer defined sequence of motherboard voltage plane connections power up routine. The NAND gates two inputs are driven by pull-up resistors. The first pull-up resistor located in the same voltage plane island as the NAND gate (P n-1) and asserts the NAND gate input high when power comes on. The second NAND gate input pull-up resistor resides in the next voltage plane island (P n) and is connected to an open collector driver (shown as a transistor on the Figure) that resides in the third next voltage plane island (P n+1). The open collector driver input is connected to a third pull up resistor that resides in the third...