Browse Prior Art Database

Testing: WLR Padsharing

IP.com Disclosure Number: IPCOM000016010D
Original Publication Date: 2002-Nov-16
Included in the Prior Art Database: 2003-Jun-21
Document File: 3 page(s) / 91K

Publishing Venue

IBM

Abstract

Title: Wafer Level Reliability: Optimization of devices in the scribe line by implementing a novel padsharing technique William R. Tonti Toshiharu Saitoh IBM MicroElectronics, Essex Junction VT 05452 1. Introduction: With each new generation of semiconductor devices, chip and die size are proportionally decreased so that corresponding chips per wafer are substantially increased. This results in severe space limitations for test structures required necessary to monitor process and device parameters. This is particularly true for (but not limited to) production phases where test structures (process and parameter control monitors) can only be placed within the dicing channel, or the scribe line used to singulate associated chips. Typically the test structures are small with respect to the associated chip and scribe line area, and can be placed between or underneath probing pads. Under this criterion the limiting factor becomes the that are physically possible to place within the scribe line. Decreasing scribe line area implies a decreasing pad availability and hence a decrease in the number of associated test structures.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 42% of the total text.

Page 1 of 3

Testing: WLR Padsharing

   Title: Wafer Level Reliability: Optimization of devices in the scribe line by implementing a novel padsharing technique

William R. Tonti Toshiharu Saitoh IBM MicroElectronics, Essex Junction VT 05452

1. Introduction:

With each new generation of semiconductor devices, chip and die size are proportionally decreased so that corresponding chips per wafer are substantially increased. This results in severe space limitations for test structures required necessary to monitor process and device parameters. This is particularly true for (but not limited to) production phases where test structures (process and parameter control monitors) can only be placed within the dicing channel, or the scribe line used to singulate associated chips. Typically the test structures are small with respect to the associated chip and scribe line area, and can be placed between or underneath probing pads. Under this criterion the limiting factor becomes the that are physically possible to place within the scribe line. Decreasing scribe line area implies a decreasing pad availability and hence a decrease in the number of associated test structures.

The goal is therefore to share (i.e. multiple use of) individual pads between separate, electrically independent structures that can be independently measured sequentially within one tester set down. In common (single gate oxide thickness) technology an complete device ensemble having geometric varying L and W is necessary and sufficient for delta L and delta W measurements, as well as providing lime control and model to hardware feedback. This completely fills a typical industry standard 25 pad set macro (corresponding to one tester set down). Standard design practice of this single gate oxide device macro implies each device contains a unique diffusion or drain terminal wired to an individual unique pad. Thus, in standard dual gate oxides employed in the industry today twice as many devices need to be tested, and hence twice as many pads and space would be necessary to wire all devices individually. This is in direct conflict with the decreasing area in the scribe line for such test structures.

2. Prior Art:

A pad sharing approach is frequently used for device parameter monitoring but limited to a common gate and common source diffusion for one set of devices. I.e., one common pad for gate voltage for each group of FETs, one common pad for source voltage for each group of FETs, and individual drain pads for each single device, and a common back gate or well pad. This approach allows one to measure a total of 22 different devices with one 25 pad set and one tester set down. In the extreme case a unique pad is defined for each transistor structure (common well), further limiting the test specification coverage.

3. Invention:

In multiple gate oxide thickness technology, for delta L and delta W measurements an entire spectrum of devices for all gate oxide thicknesses is necessary. Following the...