Browse Prior Art Database

Hub to Hub Bus

IP.com Disclosure Number: IPCOM000016045D
Original Publication Date: 2002-Jul-12
Included in the Prior Art Database: 2003-Jun-21
Document File: 7 page(s) / 81K

Publishing Venue

IBM

Abstract

1 Introduction 1.1 Overview The following described System is defined as a multi node machine. Each node consists of several Processor Chips, Cache Chips, Memory Controller Chips and IO-Chips. In addition, a single Hub Chip is assigned to each node. The Hub to Hub (HtH) bus is used to establish communication between Hub Chips in a multi-node environment. Each node consist of several processors connected to one Hub Chip. In general the HtH bus has two different usages. First, the HtH bus is used to distribute nodal information which is required System wide and therefore on all Hub Chips. Second, the HtH bus provides an access path from every processor in the System to every engine defined on a Hub Chip. Engines on a Hub Chip are defined as nodal Run-Control and Serviceability Engines to control processor chips on a node. High Level Diagram Hub Chip x Hub Chip y

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Hub to Hub Bus

1 Introduction
1.1 Overview The following described System is defined as a multi node machine. Each node consists of several Processor Chips, Cache Chips, Memory Controller Chips and IO-Chips. In addition, a single Hub Chip is assigned to each node. The Hub to Hub (HtH) bus is used to establish communication between Hub Chips in a multi-node environment. Each node consist of several processors connected to one Hub Chip. In general the HtH bus has two different usages. First, the HtH bus is used to distribute nodal information which is required System wide and therefore on all Hub Chips. Second, the HtH bus provides an access path from every processor in the System to every engine defined on a Hub Chip. Engines on a Hub Chip are defined as nodal Run-Control and Serviceability Engines to control processor chips on a node.

High Level Diagram

Hub Chip x Hub Chip y

hub_conn_x_y

hub_conn_y_x

Figure 1-1: High level Diagram

Figure 1-1 above shows a typical system configuration with two Hub Chips where the HtH bus is implemented. Without loss ordinary generality two different types of requesters / targets are described.

Req Unit 0

Req Unit 1

Target Unit 0

ctrl busTarget Unit 1

Hub to Hub Logic

Hub to Hub Logic

Req Unit 0

Req Unit 1

Target Unit 0

Target Unit 1

Malfunction

Malfunction

ctrl bus

data bus

ctrl bus

data bus

ctrl bus

data bus

ctrl bus

ctrl bus

data bus

ctrl bus

data bus

Send

Recv

data bus

data bus

0

0

#

rP eoc orss

brA i t re

1

bAr i rte

Processor #

...

...

1

15

15

moC m

moC m

Recv

Send

ctrl bus

0

0

gnE i en #

leS tce ro

1

leS tce ro

...

1

ginE en #

...

15

3

1

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Req Unit 0/Target Unit 0:

Req Unit 0 is the Run-Control logic of the Hub Chip itself. Nodal Information which is required System wide is distributed via the HtH Bus. The Req Unit 0 does not receive an acknowledge from the Target Unit 0. Req Unit 0 is just a source, Target Unit 0 is just a sink for the HtH logic. A Timing Diagram for a data transfer from Req Unit 0 to Target Unit 1 is shown in Chapter 5.1

Req Unit 1/Target Unit 1:

Req Unit 1 handles requests from all processors connected via separate bus interfaces to the Hub Chip. To avoid conflicts between processors accessing the HtH logic at the same time an arbitration logic is used to serialize processor requests. The target of processor commands (Target Unit 1) are engines defined on another Hub Chip. Engines on Hub Chips are Run-Control and Serviceability Units which serve as controlling units for processor chips on one node. The Req Unit 1 receives an acknowledge from the Target Unit 1. Therefore Req Unit 1 and Target Unit 1 must be capable to serve as source and as sink for the HtH logic. A Timing Diagram for a data transfer from Req Unit 1 to Target Unit 1 and the associated acknowledge data transfer is shown in Chapter 5.2

2 Bus Description
2.1 Overview The HtH bus is a single ended point to point bus. The HtH bus is split into tw...