Browse Prior Art Database

Automatic CSIX bus electrical interface selection

IP.com Disclosure Number: IPCOM000016060D
Original Publication Date: 2002-Jul-11
Included in the Prior Art Database: 2003-Jun-21
Document File: 3 page(s) / 54K

Publishing Venue

IBM

Abstract

The Common Switch Interface Specification (CSIX) defines a physical interface for transferring information between a traffic manager (also named Network Processor or Protocol Engine) and a switching fabric. From a hardware standpoint the CSIX physical interface defines two modes of operation, each of them having the following bus characteristics:

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Automatic CSIX bus electrical interface selection

The Common Switch Interface Specification (CSIX) defines a physical interface for transferring information between a traffic manager (also named Network Processor or Protocol Engine) and a switching fabric. From a hardware standpoint the CSIX physical interface defines two modes of operation, each of them having the following bus characteristics:

LVCMOS mode:

- the bus is 280-bit wide made of:

- 128 transmit data signals split into four groups: G0_TxD(31..0),

G1_TxD(31..0), G2_TxD(31..0), G3_TxD(31..0)

- 128 receive data signals split into four groups: G0_RxD(31..0),

G1_RxD(31..0), G2_RxD(31..0), G3_RxD(31..0)

- 12 transmit control signals, three per group: G0_TCLK, G0_TSOF,

G0_TPAR, G1_TCLK, G1_TSOF, G1_TPAR, G2_TCLK, G2_TSOF,

G2_TPAR, G3_TCLK, G3_TSOF, G3_TPAR

- 12 receive control signals, three per group: G0_RCLK, G0_RSOF,

G0_RPAR, G1_RCLK, G1_RSOF, G1_RPAR, G2_RCLK, G2_RSOF,

G2_RPAR, G3_RCLK, G3_RSOF, G3_RPAR

- the bus operates at a 125 Mhz clock provided by the traffic manager

- the electrical interface is LVCMOS. The traffic manager and the switching fabric output buffers are powered from 2.5V and a 50-ohm termination resistor is connected to ground for each receive signal

HSTL mode:

- the bus is 140-bit wide made of:

- 64 transmit data signals split into two groups: G0_TxD(31..0), G1_TxD(31..0)

- 64 receive data signals split into two groups: G0_RxD(31..0), G1_RxD(31..0)

- 6 transmit control signals, three per group: G0_TCLK, G0_TSOF, G0_TPAR,

G1_TCLK, G1_TSOF, G1_TPAR

- 6 receive control signals, three per group: G0_RCLK, G0_RSOF, G0_RPAR,

G1_RCLK, G1_RSOF, G1_RPAR

- the bus operates at a 250 Mhz clock provided by the traffic manager

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- the electrical interface is HSTL class-1. The traffic manager and the switching

fabric output buffers are powered from 1.5V and a 50-ohm termination resistor

is connected to 0.75V for each receive signal

The invention consists of detecting the speed of the clock bus generated by the traffic manager (G0_TCLK signal) and automatically providing the appropriate power supplies to both the output buffers and the termi...