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System Interrupts I/Os saving Disclosure Number: IPCOM000016076D
Original Publication Date: 2002-Jul-11
Included in the Prior Art Database: 2003-Jun-21
Document File: 3 page(s) / 79K

Publishing Venue



A. Problem description

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System Interrupts I/Os saving

A. Problem description

In present systems, when a hardware designer wants to connect a lot of interrupts from an ASIC to a microprocessor, the natural way is to use an interrupt controller already existing (of the shelf) or to use any programming device (CPLD) to make a Boolean OR equation in order to make aware the microprocessor of an interrupt event.

    In the case of an amount of more than 10 interrupts and more than two ASICs, these solutions become very huge in term of cost and real estate on the raw card.

B. Description of the invention

    The proposed solution is based (on figure) upon a modification of the interrupt system into the ASICs and a new treatment of these interrupts into a CPLD.

The function to be implemented into the ASICs is the following:

The seven (for example) interrupts are latched in the L0 o L6 latches.

int0 int1 int2 int3 int4 int5 int0int6














Load 1Shift outL13

Shift clock


    A shift register made up with the latches L7 to L13 receives in parallel the latches interrupts. A "LOAD" command loads this shit register, the "SHIFT CLOCK" composed of seven clock pulses enables the propagation of the value of the seven interrupts up to the "SHIFT OUT" serial lead.

    This macro is slave, it is to say that all the commands are given by a CPLD which function is to generate the signals by the way of a state machine (figure 2).

    In the case of several ASICs (on figure 3), we can "daisy chain" the devices and generate a burst shift clock equivalent to the total number of interrupts .

On the following figure we can...